c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
67 lines
1.5 KiB
C++
67 lines
1.5 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include "mem_sim.h"
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#include "cache_sim.h"
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#include "constants.h"
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#include "dcrs.h"
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#include "cluster.h"
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namespace vortex {
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class ProcessorImpl {
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public:
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struct PerfStats {
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uint64_t mem_reads;
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uint64_t mem_writes;
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uint64_t mem_latency;
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CacheSim::PerfStats l3cache;
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Cluster::PerfStats clusters;
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PerfStats()
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: mem_reads(0)
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, mem_writes(0)
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, mem_latency(0)
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{}
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};
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ProcessorImpl(const Arch& arch);
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~ProcessorImpl();
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void attach_ram(RAM* mem);
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int run(bool riscv_test);
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void write_dcr(uint32_t addr, uint32_t value);
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ProcessorImpl::PerfStats perf_stats() const;
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private:
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void reset();
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const Arch& arch_;
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std::vector<std::shared_ptr<Cluster>> clusters_;
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DCRS dcrs_;
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MemSim::Ptr memsim_;
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CacheSim::Ptr l3cache_;
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uint64_t perf_mem_reads_;
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uint64_t perf_mem_writes_;
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uint64_t perf_mem_latency_;
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uint64_t perf_mem_pending_reads_;
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};
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}
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