Blaise Tine 6674e8c44a cache bank area optimization + multi-porting fix for l2/l3 caches

2021-08-28 21:34:06 -07:00

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VX_bank.v

cache bank area optimization + multi-porting fix for l2/l3 caches

2021-08-28 21:34:06 -07:00

VX_cache_define.vh

cache bank area optimization + multi-porting fix for l2/l3 caches

2021-08-28 21:34:06 -07:00

VX_cache.v

cache bank area optimization + multi-porting fix for l2/l3 caches

2021-08-28 21:34:06 -07:00

VX_core_req_bank_sel.v

cache bank area optimization + multi-porting fix for l2/l3 caches

2021-08-28 21:34:06 -07:00

VX_core_rsp_merge.v

cache bank area optimization + multi-porting fix for l2/l3 caches

2021-08-28 21:34:06 -07:00

VX_data_access.v

cache area optimization by disabling BRAM read-during-write bypassing for tag/data stores

2021-08-26 12:27:38 -07:00

VX_flush_ctrl.v

refactoring cache_config

2021-05-27 14:41:46 -07:00

VX_miss_resrv.v

block ram refactoring (multi-porting supporting and simulation support)

2021-08-26 08:19:44 -07:00

VX_nc_bypass.v

cache bank area optimization + multi-porting fix for l2/l3 caches

2021-08-28 21:34:06 -07:00

VX_shared_mem.v

cache area optimization by disabling BRAM read-during-write bypassing for tag/data stores

2021-08-26 12:27:38 -07:00

VX_tag_access.v

cache bank area optimization + multi-porting fix for l2/l3 caches

2021-08-28 21:34:06 -07:00