172 lines
7.1 KiB
Verilog
172 lines
7.1 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_cache_miss_resrv #(
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parameter CACHE_ID = 0,
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parameter BANK_ID = 0,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE = 0,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 0,
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// Size of a word in bytes
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parameter WORD_SIZE = 0,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUM_REQUESTS = 0,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 0,
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// core request tag size
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parameter CORE_TAG_WIDTH = 0,
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// Snooping request tag width
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parameter SNP_REQ_TAG_WIDTH = 0
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) (
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input wire clk,
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input wire reset,
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// Miss enqueue
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input wire miss_add,
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input wire from_mrvq,
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input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr,
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input wire[`UP(`WORD_SELECT_WIDTH)-1:0] miss_add_wsel,
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input wire[`WORD_WIDTH-1:0] miss_add_data,
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input wire[`REQS_BITS-1:0] miss_add_tid,
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input wire[`REQ_TAG_WIDTH-1:0] miss_add_tag,
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input wire miss_add_rw,
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input wire[WORD_SIZE-1:0] miss_add_byteen,
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input wire mrvq_init_ready_state,
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input wire miss_add_is_snp,
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input wire miss_add_snp_invalidate,
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output wire miss_resrv_full,
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output wire miss_resrv_stop,
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// Broadcast Address
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input wire is_fill_st1,
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input wire[`LINE_ADDR_WIDTH-1:0] fill_addr_st1,
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output wire pending_hazard,
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// Miss dequeue
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input wire miss_resrv_pop,
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output wire miss_resrv_valid_st0,
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output wire[`LINE_ADDR_WIDTH-1:0] miss_resrv_addr_st0,
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output wire[`UP(`WORD_SELECT_WIDTH)-1:0] miss_resrv_wsel_st0,
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output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0,
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output wire[`REQS_BITS-1:0] miss_resrv_tid_st0,
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output wire[`REQ_TAG_WIDTH-1:0] miss_resrv_tag_st0,
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output wire miss_resrv_rw_st0,
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output wire[WORD_SIZE-1:0] miss_resrv_byteen_st0,
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output wire miss_resrv_is_snp_st0,
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output wire miss_resrv_snp_invalidate_st0
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);
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reg [`MRVQ_METADATA_WIDTH-1:0] metadata_table[MRVQ_SIZE-1:0];
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reg [MRVQ_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;
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reg [MRVQ_SIZE-1:0] valid_table;
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reg [MRVQ_SIZE-1:0] ready_table;
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reg [`LOG2UP(MRVQ_SIZE)-1:0] schedule_ptr;
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reg [`LOG2UP(MRVQ_SIZE)-1:0] head_ptr;
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reg [`LOG2UP(MRVQ_SIZE)-1:0] tail_ptr;
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reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size;
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`STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size");
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assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE));
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assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-5)); // need to add 5 cycles to prevent pipeline lock
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wire enqueue_possible = !miss_resrv_full;
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wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;
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reg [MRVQ_SIZE-1:0] make_ready;
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reg [MRVQ_SIZE-1:0] make_ready_push;
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reg [MRVQ_SIZE-1:0] valid_address_match;
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genvar i;
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generate
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for (i = 0; i < MRVQ_SIZE; i++) begin
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assign valid_address_match[i] = valid_table[i] && (addr_table[i] === fill_addr_st1);
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assign make_ready[i] = is_fill_st1 && valid_address_match[i];
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end
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endgenerate
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assign pending_hazard = |(valid_address_match);
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wire dequeue_possible = valid_table[schedule_ptr] && ready_table[schedule_ptr];
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wire [`LOG2UP(MRVQ_SIZE)-1:0] dequeue_index = schedule_ptr;
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assign miss_resrv_valid_st0 = dequeue_possible;
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assign miss_resrv_addr_st0 = addr_table[dequeue_index];
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assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_tag_st0, miss_resrv_rw_st0, miss_resrv_byteen_st0, miss_resrv_wsel_st0, miss_resrv_is_snp_st0, miss_resrv_snp_invalidate_st0} = metadata_table[dequeue_index];
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wire mrvq_push = miss_add && enqueue_possible && !from_mrvq;
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wire mrvq_pop = miss_resrv_pop && dequeue_possible;
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wire recover_state = miss_add && from_mrvq;
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wire increment_head = !miss_add && from_mrvq;
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wire update_ready = (|make_ready);
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wire qual_mrvq_init = mrvq_push && mrvq_init_ready_state;
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assign make_ready_push = (MRVQ_SIZE'(qual_mrvq_init)) << enqueue_index;
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always @(posedge clk) begin
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if (reset) begin
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valid_table <= 0;
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ready_table <= 0;
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size <= 0;
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schedule_ptr <= 0;
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head_ptr <= 0;
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tail_ptr <= 0;
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end else begin
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if (mrvq_push) begin
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valid_table[enqueue_index] <= 1;
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ready_table[enqueue_index] <= mrvq_init_ready_state;
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addr_table[enqueue_index] <= miss_add_addr;
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metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_tag, miss_add_rw, miss_add_byteen, miss_add_wsel, miss_add_is_snp, miss_add_snp_invalidate};
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tail_ptr <= tail_ptr + 1;
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end else if (increment_head) begin
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valid_table[head_ptr] <= 0;
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head_ptr <= head_ptr + 1;
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end else if (recover_state) begin
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schedule_ptr <= schedule_ptr - 1;
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end
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// update entry as 'ready' during DRAM fill response
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if (update_ready) begin
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ready_table <= ready_table | make_ready | make_ready_push;
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end
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if (mrvq_pop) begin
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ready_table[dequeue_index] <= 0;
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schedule_ptr <= schedule_ptr + 1;
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end
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if (!(mrvq_push && increment_head)) begin
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if (mrvq_push) begin
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size <= size + 1;
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end
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if (increment_head) begin
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size <= size - 1;
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end
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end
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end
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end
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`ifdef DBG_PRINT_CACHE_MSRQ
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integer j;
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always @(posedge clk) begin
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if (mrvq_push || mrvq_pop || increment_head || recover_state) begin
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$write("%t: bank%0d-%0d msrq: push=%b pop=%b incr=%d recv=%d", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop, increment_head, recover_state);
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for (j = 0; j < MRVQ_SIZE; j++) begin
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if (valid_table[j]) begin
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$write(" ");
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if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*");
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if (~ready_table[j]) $write("!");
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$write("addr%0d=%0h", j, `LINE_TO_BYTE_ADDR(addr_table[j], BANK_ID));
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end
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end
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$write("\n");
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end
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end
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`endif
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endmodule |