d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
50 lines
1.4 KiB
Systemverilog
50 lines
1.4 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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interface VX_cache_perf_if ();
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wire [`PERF_CTR_BITS-1:0] reads;
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wire [`PERF_CTR_BITS-1:0] writes;
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wire [`PERF_CTR_BITS-1:0] read_misses;
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wire [`PERF_CTR_BITS-1:0] write_misses;
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wire [`PERF_CTR_BITS-1:0] bank_stalls;
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wire [`PERF_CTR_BITS-1:0] mshr_stalls;
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wire [`PERF_CTR_BITS-1:0] mem_stalls;
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wire [`PERF_CTR_BITS-1:0] crsp_stalls;
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modport master (
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output reads,
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output writes,
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output read_misses,
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output write_misses,
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output bank_stalls,
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output mshr_stalls,
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output mem_stalls,
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output crsp_stalls
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);
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modport slave (
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input reads,
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input writes,
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input read_misses,
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input write_misses,
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input bank_stalls,
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input mshr_stalls,
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input mem_stalls,
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input crsp_stalls
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);
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endinterface
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