102 lines
2.9 KiB
Verilog
102 lines
2.9 KiB
Verilog
`include "VX_define.vh"
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module VX_fpu_unit #(
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parameter CORE_ID = 0
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) (
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// inputs
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input wire clk,
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input wire reset,
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// inputs
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VX_fpu_req_if fpu_req_if,
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VX_csr_to_fpu_if csr_to_fpu_if,
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// outputs
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VX_fpu_to_cmt_if fpu_commit_if
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);
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VX_fpu_req_if fpu_req_tmp_if();
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// resolve dynamic FRM
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wire [`FRM_BITS-1:0] frm, frm_tmp;
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assign csr_to_fpu_if.wid = fpu_req_if.wid;
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assign frm = (fpu_req_if.frm == `FRM_DYN) ? csr_to_fpu_if.frm : fpu_req_if.frm;
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// use a skid buffer since fpcore has realtime backpressure
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VX_elastic_buffer #(
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.DATAW (`ISTAG_BITS + `NW_BITS + 32 + `FPU_BITS + `FRM_BITS + (3 * `NUM_THREADS * 32)),
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.SIZE (0)
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) input_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (fpu_req_if.valid),
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.ready_in (fpu_req_if.ready),
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.data_in ({fpu_req_if.issue_tag, fpu_req_if.wid, fpu_req_if.curr_PC, fpu_req_if.op, frm, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}),
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.data_out ({fpu_req_tmp_if.issue_tag, fpu_req_tmp_if.wid, fpu_req_tmp_if.curr_PC, fpu_req_tmp_if.op, frm_tmp, fpu_req_tmp_if.rs1_data, fpu_req_tmp_if.rs2_data, fpu_req_tmp_if.rs3_data}),
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.ready_out (fpu_req_tmp_if.ready),
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.valid_out (fpu_req_tmp_if.valid)
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);
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`ifdef SYNTHESIS
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VX_fp_fpga fp_core (
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.clk (clk),
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.reset (reset),
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.valid_in (fpu_req_tmp_if.valid),
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.ready_in (fpu_req_tmp_if.ready),
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.tag_in (fpu_req_tmp_if.issue_tag),
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.op (fpu_req_tmp_if.op),
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.frm (frm_tmp),
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.dataa (fpu_req_tmp_if.rs1_data),
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.datab (fpu_req_tmp_if.rs2_data),
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.datac (fpu_req_tmp_if.rs3_data),
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.result (fpu_commit_if.data),
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.has_fflags (fpu_commit_if.has_fflags),
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.fflags (fpu_commit_if.fflags),
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.tag_out (fpu_commit_if.issue_tag),
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.ready_out (1'b1),
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.valid_out (fpu_commit_if.valid)
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);
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`else
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VX_fpnew #(
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.FMULADD (1),
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.FDIVSQRT (1),
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.FNONCOMP (1),
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.FCONV (1)
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) fp_core (
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.clk (clk),
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.reset (reset),
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.valid_in (fpu_req_tmp_if.valid),
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.ready_in (fpu_req_tmp_if.ready),
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.tag_in (fpu_req_tmp_if.issue_tag),
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.op (fpu_req_tmp_if.op),
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.frm (frm_tmp),
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.dataa (fpu_req_tmp_if.rs1_data),
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.datab (fpu_req_tmp_if.rs2_data),
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.datac (fpu_req_tmp_if.rs3_data),
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.result (fpu_commit_if.data),
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.has_fflags (fpu_commit_if.has_fflags),
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.fflags (fpu_commit_if.fflags),
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.tag_out (fpu_commit_if.issue_tag),
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.ready_out (1'b1),
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.valid_out (fpu_commit_if.valid)
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);
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`endif
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endmodule |