d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
41 lines
1.2 KiB
Systemverilog
41 lines
1.2 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_bits_insert #(
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parameter N = 1,
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parameter S = 1,
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parameter POS = 0
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) (
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input wire [N-1:0] data_in,
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input wire [`UP(S)-1:0] sel_in,
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output wire [N+S-1:0] data_out
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);
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if (S == 0) begin
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`UNUSED_VAR (sel_in)
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assign data_out = data_in;
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end else begin
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if (POS == 0) begin
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assign data_out = {data_in, sel_in};
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end else if (POS == N) begin
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assign data_out = {sel_in, data_in};
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end else begin
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assign data_out = {data_in[N-1:POS], sel_in, data_in[POS-1:0]};
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end
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end
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endmodule
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`TRACING_ON
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