c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
116 lines
2.6 KiB
C++
116 lines
2.6 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <iostream>
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#include <fstream>
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#include <iomanip>
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#include <unistd.h>
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#include <util.h>
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#include <mem.h>
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#include <VX_config.h>
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#include <VX_types.h>
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#include "processor.h"
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#define RAM_PAGE_SIZE 4096
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using namespace vortex;
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static void show_usage() {
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std::cout << "Usage: [-r: riscv-test] [-h: help] <program>" << std::endl;
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}
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bool riscv_test = false;
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const char* program = nullptr;
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static void parse_args(int argc, char **argv) {
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int c;
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while ((c = getopt(argc, argv, "rh?")) != -1) {
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switch (c) {
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case 'r':
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riscv_test = true;
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break;
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case 'h':
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case '?':
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show_usage();
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exit(0);
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break;
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default:
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show_usage();
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exit(-1);
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}
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}
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if (optind < argc) {
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program = argv[optind];
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std::cout << "Running " << program << "..." << std::endl;
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} else {
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show_usage();
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exit(-1);
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}
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}
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int main(int argc, char **argv) {
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int exitcode = 0;
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parse_args(argc, argv);
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// create memory module
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vortex::RAM ram(RAM_PAGE_SIZE);
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// create processor
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vortex::Processor processor;
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// attach memory module
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processor.attach_ram(&ram);
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// setup base DCRs
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const uint64_t startup_addr(STARTUP_ADDR);
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processor.write_dcr(VX_DCR_BASE_STARTUP_ADDR0, startup_addr & 0xffffffff);
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#if (XLEN == 64)
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processor.write_dcr(VX_DCR_BASE_STARTUP_ADDR1, startup_addr >> 32);
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#endif
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processor.write_dcr(VX_DCR_BASE_MPM_CLASS, 0);
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// load program
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{
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std::string program_ext(fileExtension(program));
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if (program_ext == "bin") {
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ram.loadBinImage(program, startup_addr);
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} else if (program_ext == "hex") {
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ram.loadHexImage(program);
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} else {
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std::cout << "*** error: only *.bin or *.hex images supported." << std::endl;
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return -1;
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}
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}
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// run simulation
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exitcode = processor.run();
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if (riscv_test) {
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if (1 == exitcode) {
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std::cout << "Passed" << std::endl;
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exitcode = 0;
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} else {
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std::cout << "Failed" << std::endl;
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exitcode = 1;
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}
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} else {
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if (exitcode != 0) {
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std::cout << "*** error: exitcode=" << exitcode << std::endl;
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}
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}
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return exitcode;
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}
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