Blaise Tine bdfacf709c yosys synthesis refactoring

2020-07-10 18:56:41 -04:00

..

cache

minor update

2020-06-28 22:58:18 -07:00

core

yosys synthesis refactoring

2020-07-10 18:56:41 -04:00

pipeline

yosys synthesis refactoring

2020-07-10 18:56:41 -04:00

top

yosys synthesis refactoring

2020-07-10 18:56:41 -04:00

vortex

yosys synthesis refactoring

2020-07-10 18:56:41 -04:00

.gitignore

minor update

2020-06-29 15:09:14 -07:00

project.sdc

set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18

2020-06-29 08:03:19 -07:00

project.tcl

driver basic test and demo test refactoring

2020-06-19 09:12:07 -07:00

timing.tcl

driver basic test and demo test refactoring

2020-06-19 09:12:07 -07:00