626 lines
16 KiB
C++
626 lines
16 KiB
C++
#include <iostream>
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#include <string>
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#include <stdlib.h>
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#include <string.h>
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#include <iomanip>
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#include <vector>
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#include <unordered_map>
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#include <util.h>
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#include "debug.h"
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#include "types.h"
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#include "decode.h"
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#include "archdef.h"
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#include "instr.h"
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using namespace vortex;
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struct InstTableEntry_t {
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bool controlFlow;
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InstType iType;
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};
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static const std::unordered_map<int, struct InstTableEntry_t> sc_instTable = {
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{Opcode::NOP, {false, InstType::N_TYPE}},
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{Opcode::R_INST, {false, InstType::R_TYPE}},
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{Opcode::L_INST, {false, InstType::I_TYPE}},
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{Opcode::I_INST, {false, InstType::I_TYPE}},
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{Opcode::S_INST, {false, InstType::S_TYPE}},
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{Opcode::B_INST, {true , InstType::B_TYPE}},
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{Opcode::LUI_INST, {false, InstType::U_TYPE}},
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{Opcode::AUIPC_INST, {false, InstType::U_TYPE}},
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{Opcode::JAL_INST, {true , InstType::J_TYPE}},
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{Opcode::JALR_INST, {true , InstType::I_TYPE}},
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{Opcode::SYS_INST, {true , InstType::I_TYPE}},
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{Opcode::FENCE, {true , InstType::I_TYPE}},
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{Opcode::FL, {false, InstType::I_TYPE}},
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{Opcode::FS, {false, InstType::S_TYPE}},
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{Opcode::FCI, {false, InstType::R_TYPE}},
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{Opcode::FMADD, {false, InstType::R4_TYPE}},
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{Opcode::FMSUB, {false, InstType::R4_TYPE}},
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{Opcode::FMNMADD, {false, InstType::R4_TYPE}},
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{Opcode::FMNMSUB, {false, InstType::R4_TYPE}},
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{Opcode::VSET, {false, InstType::V_TYPE}},
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{Opcode::GPGPU, {false, InstType::R_TYPE}},
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{Opcode::GPU, {false, InstType::R4_TYPE}},
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{Opcode::R_INST_64, {false, InstType::R_TYPE}},
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{Opcode::I_INST_64, {false, InstType::I_TYPE}},
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};
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static const char* op_string(const Instr &instr) {
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auto opcode = instr.getOpcode();
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Word func2 = instr.getFunc2();
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Word func3 = instr.getFunc3();
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Word func7 = instr.getFunc7();
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Word rs2 = instr.getRSrc(1);
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XWord imm = instr.getImm();
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switch (opcode) {
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case Opcode::NOP: return "NOP";
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case Opcode::LUI_INST: return "LUI";
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case Opcode::AUIPC_INST: return "AUIPC";
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case Opcode::R_INST:
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if (func7 & 0x1) {
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switch (func3) {
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case 0: return "MUL";
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case 1: return "MULH";
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case 2: return "MULHSU";
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case 3: return "MULHU";
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case 4: return "DIV";
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case 5: return "DIVU";
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case 6: return "REM";
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case 7: return "REMU";
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}
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} else {
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switch (func3) {
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case 0: return func7 ? "SUB" : "ADD";
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case 1: return "SLL";
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case 2: return "SLT";
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case 3: return "SLTU";
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case 4: return "XOR";
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case 5: return func7 ? "SRA" : "SRL";
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case 6: return "OR";
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case 7: return "AND";
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}
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}
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case Opcode::I_INST:
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switch (func3) {
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case 0: return "ADDI";
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case 1: return "SLLI";
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case 2: return "SLTI";
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case 3: return "SLTIU";
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case 4: return "XORI";
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case 5: return func7 ? "SRAI" : "SRLI";
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case 6: return "ORI";
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case 7: return "ANDI";
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}
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case Opcode::B_INST:
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switch (func3) {
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case 0: return "BEQ";
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case 1: return "BNE";
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case 4: return "BLT";
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case 5: return "BGE";
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case 6: return "BLTU";
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case 7: return "BGEU";
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default:
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std::abort();
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}
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case Opcode::JAL_INST: return "JAL";
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case Opcode::JALR_INST: return "JALR";
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case Opcode::L_INST:
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switch (func3) {
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case 0: return "LBI";
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case 1: return "LHI";
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case 2: return "LW";
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case 3: return "LD";
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case 4: return "LBU";
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case 5: return "LHU";
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case 6: return "LWU";
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default:
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std::abort();
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}
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case Opcode::S_INST:
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switch (func3) {
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case 0: return "SB";
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case 1: return "SH";
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case 2: return "SW";
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case 3: return "SD";
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default:
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std::abort();
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}
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case Opcode::R_INST_64:
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if (func7 & 0x1){
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switch (func3) {
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case 0: return func7 ? "SUBW" : "ADDW";
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case 1: return "SLLW";
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case 5: return func7 ? "SRAW" : "SRLW";
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default:
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std::abort();
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}
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} else {
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switch (func3) {
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case 0: return "MULW";
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case 4: return "DIVW";
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case 5: return "DIVUW";
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case 6: return "REMW";
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case 7: return "REMUW";
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default:
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std::abort();
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}
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}
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case Opcode::I_INST_64:
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switch (func3) {
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case 0: return "ADDIW";
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case 1: return "SLLIW";
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case 5: return func7 ? "SRAIW" : "SRLIW";
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default:
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std::abort();
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}
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case Opcode::SYS_INST:
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switch (func3) {
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case 0:
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switch (imm) {
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case 0x000: return "ECALL";
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case 0x001: return "EBREAK";
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case 0x002: return "URET";
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case 0x102: return "SRET";
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case 0x302: return "MRET";
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default:
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std::abort();
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}
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case 1: return "CSRRW";
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case 2: return "CSRRS";
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case 3: return "CSRRC";
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case 5: return "CSRRWI";
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case 6: return "CSRRSI";
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case 7: return "CSRRCI";
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default:
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std::abort();
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}
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case Opcode::FENCE: return "FENCE";
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case Opcode::FL:
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switch (func3) {
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case 0x1: return "VL";
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case 0x2: return "FLW";
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case 0x3: return "FLD";
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default:
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std::abort();
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}
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case Opcode::FS:
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switch (func3) {
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case 0x1: return "VS";
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case 0x2: return "FSW";
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case 0x3: return "FSD";
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default:
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std::abort();
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}
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case Opcode::FCI:
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switch (func7) {
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case 0x00: return "FADD.S";
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case 0x01: return "FADD.D";
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case 0x04: return "FSUB.S";
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case 0x05: return "FSUB.D";
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case 0x08: return "FMUL.S";
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case 0x09: return "FMUL.D";
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case 0x0c: return "FDIV.S";
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case 0x0d: return "FDIV.D";
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case 0x2c: return "FSQRT.S";
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case 0x2d: return "FSQRT.D";
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case 0x10:
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switch (func3) {
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case 0: return "FSGNJ.S";
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case 1: return "FSGNJN.S";
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case 2: return "FSGNJX.S";
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default:
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std::abort();
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}
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case 0x11:
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switch (func3) {
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case 0: return "FSGNJ.D";
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case 1: return "FSGNJN.D";
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case 2: return "FSGNJX.D";
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default:
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std::abort();
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}
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case 0x14:
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switch (func3) {
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case 0: return "FMIN.S";
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case 1: return "FMAX.S";
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default:
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std::abort();
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}
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case 0x15:
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switch (func3) {
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case 0: return "FMIN.D";
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case 1: return "FMAX.D";
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default:
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std::abort();
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}
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case 0x20: return "FCVT.S.D";
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case 0x21: return "FCVT.D.S";
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case 0x50:
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switch (func3) {
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case 0: return "FLE.S";
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case 1: return "FLT.S";
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case 2: return "FEQ.S";
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default:
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std::abort();
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}
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case 0x51:
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switch (func3) {
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case 0: return "FLE.D";
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case 1: return "FLT.D";
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case 2: return "FEQ.D";
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default:
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std::abort();
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}
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case 0x60:
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switch (rs2) {
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case 0: return "FCVT.W.S";
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case 1: return "FCVT.WU.S";
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case 2: return "FCVT.L.S";
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case 3: return "FCVT.LU.S";
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default:
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std::abort();
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}
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case 0x61:
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switch (rs2) {
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case 0: return "FCVT.W.D";
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case 1: return "FCVT.WU.D";
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case 2: return "FCVT.L.D";
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case 3: return "FCVT.LU.D";
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default:
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std::abort();
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}
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case 0x68:
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switch (rs2) {
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case 0: return "FCVT.S.W";
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case 1: return "FCVT.S.WU";
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case 2: return "FCVT.S.L";
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case 3: return "FCVT.S.LU";
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default:
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std::abort();
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}
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case 0x69:
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switch (rs2) {
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case 0: return "FCVT.D.W";
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case 1: return "FCVT.D.WU";
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case 2: return "FCVT.D.L";
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case 3: return "FCVT.D.LU";
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default:
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std::abort();
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}
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case 0x70: return func3 ? "FCLASS.S" : "FMV.X.W";
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case 0x71: return func3 ? "FCLASS.D" : "FMV.X.D";
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case 0x78: return "FMV.W.X";
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case 0x79: return "FMV.D.X";
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default:
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std::abort();
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}
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case Opcode::FMADD: return func2 ? "FMADD.D" : "FMADD.S";
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case Opcode::FMSUB: return func2 ? "FMSUB.D" : "FMSUB.S";
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case Opcode::FMNMADD: return func2 ? "FNMADD.D" : "FNMADD.S";
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case Opcode::FMNMSUB: return func2 ? "FNMSUB.D" : "FNMSUB.S";
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case Opcode::VSET: return "VSET";
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case Opcode::GPGPU:
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switch (func3) {
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case 0: return "TMC";
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case 1: return "WSPAWN";
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case 2: return "SPLIT";
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case 3: return "JOIN";
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case 4: return "BAR";
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case 5: return "PREFETCH";
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default:
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std::abort();
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}
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case Opcode::GPU:
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switch (func3) {
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case 0: return "TEX";
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case 1: {
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switch (func2) {
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case 0: return "CMOV";
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default:
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std::abort();
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}
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}
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default:
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std::abort();
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}
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default:
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std::abort();
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}
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}
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namespace vortex {
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std::ostream &operator<<(std::ostream &os, const Instr &instr) {
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auto opcode = instr.getOpcode();
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Word func2 = instr.getFunc2();
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Word func3 = instr.getFunc3();
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os << op_string(instr) << ": ";
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if (opcode == S_INST
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|| opcode == FS) {
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os << "M[r" << std::dec << instr.getRSrc(0) << " + 0x" << std::hex << instr.getImm() << "] <- ";
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os << instr.getRSType(1) << std::dec << instr.getRSrc(1);
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} else
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if (opcode == L_INST
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|| opcode == FL) {
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os << instr.getRDType() << std::dec << instr.getRDest() << " <- ";
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os << "M[r" << std::dec << instr.getRSrc(0) << " + 0x" << std::hex << instr.getImm() << "]";
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} else {
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if (instr.getRDType() != RegType::None) {
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os << instr.getRDType() << std::dec << instr.getRDest() << " <- ";
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}
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int i = 0;
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for (; i < instr.getNRSrc(); ++i) {
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if (i) os << ", ";
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os << instr.getRSType(i) << std::dec << instr.getRSrc(i);
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}
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if (instr.hasImm()) {
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if (i) os << ", ";
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os << "imm=0x" << std::hex << instr.getImm();
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}
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if (opcode == GPU && func3 == 0) {
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os << ", unit=" << std::dec << func2;
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}
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}
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return os;
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}
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}
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Decoder::Decoder(const ArchDef &arch) {
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inst_s_ = arch.wsize() * 8;
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opcode_s_ = 7;
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reg_s_ = 5;
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func2_s_ = 2;
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func3_s_ = 3;
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mop_s_ = 3;
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vmask_s_ = 1;
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shift_opcode_ = 0;
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shift_rd_ = opcode_s_;
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shift_func3_ = shift_rd_ + reg_s_;
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shift_rs1_ = shift_func3_ + func3_s_;
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shift_rs2_ = shift_rs1_ + reg_s_;
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shift_func2_ = shift_rs2_ + reg_s_;
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shift_func7_ = shift_rs2_ + reg_s_;
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shift_rs3_ = shift_func7_ + func2_s_;
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shift_vmop_ = shift_func7_ + vmask_s_;
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shift_vnf_ = shift_vmop_ + mop_s_;
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shift_func6_ = shift_func7_ + 1;
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shift_vset_ = shift_func7_ + 6;
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reg_mask_ = 0x1f;
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func2_mask_ = 0x3;
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func3_mask_ = 0x7;
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func6_mask_ = 0x3f;
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func7_mask_ = 0x7f;
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opcode_mask_ = 0x7f;
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i_imm_mask_ = 0xfff;
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s_imm_mask_ = 0xfff;
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b_imm_mask_ = 0x1fff;
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u_imm_mask_ = 0xfffff;
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j_imm_mask_ = 0xfffff;
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v_imm_mask_ = 0x7ff;
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}
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std::shared_ptr<Instr> Decoder::decode(Word code) const {
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auto instr = std::make_shared<Instr>();
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Opcode op = (Opcode)((code >> shift_opcode_) & opcode_mask_);
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instr->setOpcode(op);
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Word func2 = (code >> shift_func2_) & func2_mask_;
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Word func3 = (code >> shift_func3_) & func3_mask_;
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Word func6 = (code >> shift_func6_) & func6_mask_;
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Word func7 = (code >> shift_func7_) & func7_mask_;
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int rd = (code >> shift_rd_) & reg_mask_;
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int rs1 = (code >> shift_rs1_) & reg_mask_;
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int rs2 = (code >> shift_rs2_) & reg_mask_;
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int rs3 = (code >> shift_rs3_) & reg_mask_;
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auto op_it = sc_instTable.find(op);
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if (op_it == sc_instTable.end()) {
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std::cout << std::hex << "Error: invalid opcode: 0x" << op << std::endl;
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return nullptr;
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}
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auto iType = op_it->second.iType;
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if (op == Opcode::FL || op == Opcode::FS) {
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if (func3 != 0x2 && func3 != 0x3) {
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iType = InstType::V_TYPE;
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}
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}
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switch (iType) {
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case InstType::N_TYPE:
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break;
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case InstType::R_TYPE:
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if (op == Opcode::FCI) {
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switch (func7) {
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case 0x68: // FCVT.S.W, FCVT.S.WU, FCVT.S.L, FCVT.S.LU
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case 0x69: // FCVT.D.W, FCVT.D.WU, FCVT.D.L, FCVT.D.LU
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case 0x78: // FMV.W.X
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case 0x79: // FMV.D.X
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instr->setSrcReg(rs1);
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break;
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default:
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instr->setSrcFReg(rs1);
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}
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instr->setSrcFReg(rs2);
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switch (func7) {
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case 0x50: // FLE.S, FLT.S, FEQ.S
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case 0x51: // FLE.D, FLT.D, FEQ.D
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case 0x60: // FCVT.WU.S, FCVT.W.S, FCVT.L.S, FCVT.LU.S
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case 0x61: // FCVT.W.D, FCVT.WU.D, FCVT.L.D, FCVT.LU.D
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case 0x70: // FLASS.S, FMV.X.W
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case 0x71: // FCLASS.D, FMV.X.D
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instr->setDestReg(rd);
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break;
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default:
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instr->setDestFReg(rd);
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}
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} else {
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instr->setDestReg(rd);
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instr->setSrcReg(rs1);
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instr->setSrcReg(rs2);
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}
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instr->setFunc3(func3);
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instr->setFunc7(func7);
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break;
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case InstType::I_TYPE: {
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instr->setSrcReg(rs1);
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if (op == Opcode::FL) {
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instr->setDestFReg(rd);
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} else {
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instr->setDestReg(rd);
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}
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instr->setFunc3(func3);
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instr->setFunc7(func7);
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switch (op) {
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case Opcode::SYS_INST:
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case Opcode::FENCE:
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// uint12
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instr->setImm(code >> shift_rs2_);
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break;
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case Opcode::I_INST:
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if (func3 == 0x1 || func3 == 0x5) {
|
|
// int5 (XLEN = 32) / int6 (XLEN = 64)
|
|
int shamt_width = log2up(XLEN);
|
|
int shamt = ((func7 & 0x1) << 5) | rs2;
|
|
instr->setImm(sext(shamt, shamt_width));
|
|
} else {
|
|
// int12
|
|
instr->setImm(sext(code >> shift_rs2_, 12));
|
|
}
|
|
break;
|
|
case Opcode::I_INST_64:
|
|
if (func3 == 0x1 || func3 == 0x5) {
|
|
// int5
|
|
instr->setImm(sext64(rs2, 5));
|
|
} else {
|
|
// int12
|
|
instr->setImm(sext64(code >> shift_rs2_, 12));
|
|
}
|
|
break;
|
|
default:
|
|
// int12
|
|
instr->setImm(sext(code >> shift_rs2_, 12));
|
|
break;
|
|
}
|
|
} break;
|
|
case InstType::S_TYPE: {
|
|
instr->setSrcReg(rs1);
|
|
if (op == Opcode::FS) {
|
|
instr->setSrcFReg(rs2);
|
|
} else {
|
|
instr->setSrcReg(rs2);
|
|
}
|
|
instr->setFunc3(func3);
|
|
XWord imm = (func7 << reg_s_) | rd;
|
|
instr->setImm(sext(imm, 12));
|
|
} break;
|
|
|
|
case InstType::B_TYPE: {
|
|
instr->setSrcReg(rs1);
|
|
instr->setSrcReg(rs2);
|
|
instr->setFunc3(func3);
|
|
Word bit_11 = rd & 0x1;
|
|
Word bits_4_1 = rd >> 1;
|
|
Word bit_10_5 = func7 & 0x3f;
|
|
Word bit_12 = func7 >> 6;
|
|
XWord imm = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
|
|
instr->setImm(sext(imm, 13));
|
|
} break;
|
|
|
|
case InstType::U_TYPE:
|
|
instr->setDestReg(rd);
|
|
instr->setImm(sext(code >> shift_func3_, 20));
|
|
break;
|
|
|
|
case InstType::J_TYPE: {
|
|
instr->setDestReg(rd);
|
|
Word unordered = code >> shift_func3_;
|
|
Word bits_19_12 = unordered & 0xff;
|
|
Word bit_11 = (unordered >> 8) & 0x1;
|
|
Word bits_10_1 = (unordered >> 9) & 0x3ff;
|
|
Word bit_20 = (unordered >> 19) & 0x1;
|
|
XWord imm = (XWord) 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
|
|
if (bit_20) {
|
|
imm |= ~j_imm_mask_;
|
|
}
|
|
instr->setImm(imm);
|
|
} break;
|
|
|
|
case InstType::V_TYPE:
|
|
switch (op) {
|
|
case Opcode::VSET: {
|
|
instr->setDestVReg(rd);
|
|
instr->setSrcVReg(rs1);
|
|
instr->setFunc3(func3);
|
|
if (func3 == 7) {
|
|
instr->setImm(!(code >> shift_vset_));
|
|
if (instr->getImm()) {
|
|
Word immed = (code >> shift_rs2_) & v_imm_mask_;
|
|
instr->setImm(immed);
|
|
instr->setVlmul(immed & 0x3);
|
|
instr->setVediv((immed >> 4) & 0x3);
|
|
instr->setVsew((immed >> 2) & 0x3);
|
|
} else {
|
|
instr->setSrcVReg(rs2);
|
|
}
|
|
} else {
|
|
instr->setSrcVReg(rs2);
|
|
instr->setVmask((code >> shift_func7_) & 0x1);
|
|
instr->setFunc6(func6);
|
|
}
|
|
} break;
|
|
|
|
case Opcode::FL:
|
|
instr->setDestVReg(rd);
|
|
instr->setSrcVReg(rs1);
|
|
instr->setVlsWidth(func3);
|
|
instr->setSrcVReg(rs2);
|
|
instr->setVmask(code >> shift_func7_);
|
|
instr->setVmop((code >> shift_vmop_) & func3_mask_);
|
|
instr->setVnf((code >> shift_vnf_) & func3_mask_);
|
|
break;
|
|
|
|
case Opcode::FS:
|
|
instr->setVs3(rd);
|
|
instr->setSrcVReg(rs1);
|
|
instr->setVlsWidth(func3);
|
|
instr->setSrcVReg(rs2);
|
|
instr->setVmask(code >> shift_func7_);
|
|
instr->setVmop((code >> shift_vmop_) & func3_mask_);
|
|
instr->setVnf((code >> shift_vnf_) & func3_mask_);
|
|
break;
|
|
|
|
default:
|
|
std::abort();
|
|
}
|
|
break;
|
|
case R4_TYPE:
|
|
if (op == Opcode::GPU) {
|
|
instr->setDestReg(rd);
|
|
instr->setSrcReg(rs1);
|
|
instr->setSrcReg(rs2);
|
|
instr->setSrcReg(rs3);
|
|
} else {
|
|
instr->setDestFReg(rd);
|
|
instr->setSrcFReg(rs1);
|
|
instr->setSrcFReg(rs2);
|
|
instr->setSrcFReg(rs3);
|
|
}
|
|
instr->setFunc2(func2);
|
|
instr->setFunc3(func3);
|
|
break;
|
|
default:
|
|
std::abort();
|
|
}
|
|
|
|
return instr;
|
|
}
|