40 lines
1.3 KiB
INI
40 lines
1.3 KiB
INI
load_package flow
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set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
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set_global_assignment -name VERILOG_FILE ../VX_gpr.v
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set_global_assignment -name SDC_FILE vortex.sdc
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 80
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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# pins configuration
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package require cmdline
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proc make_all_pins_virtual { args } {
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set options {\
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{ "exclude.arg" "" "List of signals to exclude" } \
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}
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array set opts [::cmdline::getoptions quartus(args) $options]
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remove_all_instance_assignments -name VIRTUAL_PIN
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execute_module -tool map
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set name_ids [get_names -filter * -node_type pin]
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foreach_in_collection name_id $name_ids {
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set pin_name [get_name_info -info full_path $name_id]
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if { -1 == [lsearch -exact $opts(excludes) $pin_name] } {
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post_message "Making VIRTUAL_PIN assignment to $pin_name"
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set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
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} else {
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post_message "Skipping VIRTUAL_PIN assignment to $pin_name"
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}
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}
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export_assignments
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}
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make_all_pins_virtual -exclude { clk, reset } |