331 lines
14 KiB
Verilog
331 lines
14 KiB
Verilog
`include "VX_cache_define.vh"
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module VX_nc_bypass #(
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parameter NUM_REQS = 1,
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parameter NUM_RSP_TAGS = 0,
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parameter NC_TAG_BIT = 0,
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parameter CORE_ADDR_WIDTH = 1,
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parameter CORE_DATA_SIZE = 1,
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parameter CORE_TAG_IN_WIDTH = 1,
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parameter MEM_ADDR_WIDTH = 1,
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parameter MEM_DATA_SIZE = 1,
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parameter MEM_TAG_IN_WIDTH = 1,
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parameter MEM_TAG_OUT_WIDTH = 1,
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localparam CORE_DATA_WIDTH = CORE_DATA_SIZE * 8,
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localparam MEM_DATA_WIDTH = MEM_DATA_SIZE * 8,
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localparam CORE_TAG_OUT_WIDTH = CORE_TAG_IN_WIDTH - 1
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) (
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input wire clk,
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input wire reset,
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// Core request in
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input wire [NUM_REQS-1:0] core_req_valid_in,
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input wire [NUM_REQS-1:0] core_req_rw_in,
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input wire [NUM_REQS-1:0][CORE_ADDR_WIDTH-1:0] core_req_addr_in,
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input wire [NUM_REQS-1:0][CORE_DATA_SIZE-1:0] core_req_byteen_in,
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input wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_req_data_in,
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input wire [NUM_REQS-1:0][CORE_TAG_IN_WIDTH-1:0] core_req_tag_in,
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output wire [NUM_REQS-1:0] core_req_ready_in,
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// Core request out
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output wire [NUM_REQS-1:0] core_req_valid_out,
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output wire [NUM_REQS-1:0] core_req_rw_out,
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output wire [NUM_REQS-1:0][CORE_ADDR_WIDTH-1:0] core_req_addr_out,
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output wire [NUM_REQS-1:0][CORE_DATA_SIZE-1:0] core_req_byteen_out,
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output wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_req_data_out,
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output wire [NUM_REQS-1:0][CORE_TAG_OUT_WIDTH-1:0] core_req_tag_out,
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input wire [NUM_REQS-1:0] core_req_ready_out,
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// Core response in
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input wire [NUM_RSP_TAGS-1:0] core_rsp_valid_in,
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input wire [NUM_REQS-1:0] core_rsp_tmask_in,
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input wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_rsp_data_in,
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input wire [NUM_RSP_TAGS-1:0][CORE_TAG_OUT_WIDTH-1:0] core_rsp_tag_in,
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output wire [NUM_RSP_TAGS-1:0] core_rsp_ready_in,
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// Core response out
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output wire [NUM_RSP_TAGS-1:0] core_rsp_valid_out,
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output wire [NUM_REQS-1:0] core_rsp_tmask_out,
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output wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_rsp_data_out,
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output wire [NUM_RSP_TAGS-1:0][CORE_TAG_IN_WIDTH-1:0] core_rsp_tag_out,
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input wire [NUM_RSP_TAGS-1:0] core_rsp_ready_out,
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// Memory request in
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input wire mem_req_valid_in,
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input wire mem_req_rw_in,
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input wire [MEM_ADDR_WIDTH-1:0] mem_req_addr_in,
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input wire [MEM_DATA_SIZE-1:0] mem_req_byteen_in,
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input wire [MEM_DATA_WIDTH-1:0] mem_req_data_in,
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input wire [MEM_TAG_IN_WIDTH-1:0] mem_req_tag_in,
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output wire mem_req_ready_in,
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// Memory request out
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output wire mem_req_valid_out,
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output wire mem_req_rw_out,
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output wire [MEM_ADDR_WIDTH-1:0] mem_req_addr_out,
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output wire [MEM_DATA_SIZE-1:0] mem_req_byteen_out,
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output wire [MEM_DATA_WIDTH-1:0] mem_req_data_out,
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output wire [MEM_TAG_OUT_WIDTH-1:0] mem_req_tag_out,
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input wire mem_req_ready_out,
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// Memory response in
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input wire mem_rsp_valid_in,
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input wire [MEM_DATA_WIDTH-1:0] mem_rsp_data_in,
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input wire [MEM_TAG_OUT_WIDTH-1:0] mem_rsp_tag_in,
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output wire mem_rsp_ready_in,
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// Memory response out
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output wire mem_rsp_valid_out,
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output wire [MEM_DATA_WIDTH-1:0] mem_rsp_data_out,
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output wire [MEM_TAG_IN_WIDTH-1:0] mem_rsp_tag_out,
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input wire mem_rsp_ready_out
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);
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`STATIC_ASSERT((NUM_RSP_TAGS == 1 || NUM_RSP_TAGS == NUM_REQS), ("invalid paramter"))
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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localparam CORE_REQ_TIDW = $clog2(NUM_REQS);
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localparam MUX_DATAW = CORE_TAG_IN_WIDTH + CORE_DATA_WIDTH + CORE_DATA_SIZE + CORE_ADDR_WIDTH + 1;
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localparam CORE_LDATAW = $clog2(CORE_DATA_WIDTH);
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localparam MEM_LDATAW = $clog2(MEM_DATA_WIDTH);
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localparam D = MEM_LDATAW - CORE_LDATAW;
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localparam P = 2**D;
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// core request handling
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wire [NUM_REQS-1:0] core_req_valid_in_nc;
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wire [NUM_REQS-1:0] core_req_nc_sel;
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wire [NUM_REQS-1:0] core_req_nc_tids;
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wire [`UP(CORE_REQ_TIDW)-1:0] core_req_nc_tid;
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wire core_req_nc_valid;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_req_nc_tids[i] = core_req_tag_in[i][NC_TAG_BIT];
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end
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assign core_req_valid_in_nc = core_req_valid_in & core_req_nc_tids;
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VX_priority_encoder #(
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.N (NUM_REQS)
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) core_req_sel (
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.data_in (core_req_valid_in_nc),
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.index (core_req_nc_tid),
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.onehot (core_req_nc_sel),
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.valid_out (core_req_nc_valid)
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);
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assign core_req_valid_out = core_req_valid_in & ~core_req_nc_tids;
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assign core_req_rw_out = core_req_rw_in;
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assign core_req_addr_out = core_req_addr_in;
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assign core_req_byteen_out = core_req_byteen_in;
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assign core_req_data_out = core_req_data_in;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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VX_bits_remove #(
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.N (CORE_TAG_IN_WIDTH),
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.S (1),
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.POS (NC_TAG_BIT)
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) core_req_tag_remove (
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.data_in (core_req_tag_in[i]),
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.data_out (core_req_tag_out[i])
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);
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end
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if (NUM_REQS > 1) begin
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_req_ready_in[i] = core_req_valid_in_nc[i] ?
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(~mem_req_valid_in && mem_req_ready_out && core_req_nc_sel[i]) : core_req_ready_out[i];
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end
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end else begin
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`UNUSED_VAR (core_req_nc_sel)
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assign core_req_ready_in = core_req_valid_in_nc ? (~mem_req_valid_in && mem_req_ready_out) : core_req_ready_out;
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end
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// memory request handling
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assign mem_req_valid_out = mem_req_valid_in || core_req_nc_valid;
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assign mem_req_ready_in = mem_req_ready_out;
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wire [(MEM_TAG_IN_WIDTH+1)-1:0] mem_req_tag_in_nc;
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VX_bits_insert #(
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.N (MEM_TAG_IN_WIDTH),
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.S (1),
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.POS (NC_TAG_BIT)
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) mem_req_tag_insert (
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.data_in (mem_req_tag_in),
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.sel_in ('0),
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.data_out (mem_req_tag_in_nc)
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);
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if (NUM_REQS > 1) begin
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wire [CORE_TAG_IN_WIDTH-1:0] core_req_tag_in_sel;
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wire [CORE_DATA_WIDTH-1:0] core_req_data_in_sel;
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wire [CORE_DATA_SIZE-1:0] core_req_byteen_in_sel;
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wire [CORE_ADDR_WIDTH-1:0] core_req_addr_in_sel;
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wire core_req_rw_in_sel;
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wire [NUM_REQS-1:0][MUX_DATAW-1:0] core_req_nc_mux_in;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_req_nc_mux_in[i] = {core_req_tag_in[i], core_req_data_in[i], core_req_byteen_in[i], core_req_addr_in[i], core_req_rw_in[i]};
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end
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VX_onehot_mux #(
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.DATAW (MUX_DATAW),
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.N (NUM_REQS)
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) core_req_nc_mux (
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.data_in (core_req_nc_mux_in),
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.sel_in (core_req_nc_sel),
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.data_out ({core_req_tag_in_sel, core_req_data_in_sel, core_req_byteen_in_sel, core_req_addr_in_sel, core_req_rw_in_sel})
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);
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assign mem_req_rw_out = mem_req_valid_in ? mem_req_rw_in : core_req_rw_in_sel;
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assign mem_req_addr_out = mem_req_valid_in ? mem_req_addr_in : core_req_addr_in_sel[D +: MEM_ADDR_WIDTH];
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for (genvar i = 0; i < P; ++i) begin
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assign mem_req_data_out[i * CORE_DATA_WIDTH +: CORE_DATA_WIDTH] = mem_req_valid_in ?
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mem_req_data_in[i * CORE_DATA_WIDTH +: CORE_DATA_WIDTH] : core_req_data_in_sel;
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end
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if (D != 0) begin
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wire [D-1:0] req_addr_idx = core_req_addr_in_sel[D-1:0];
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reg [MEM_DATA_SIZE-1:0] mem_req_byteen_in_r;
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always @(*) begin
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mem_req_byteen_in_r = 0;
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mem_req_byteen_in_r[req_addr_idx * CORE_DATA_SIZE +: CORE_DATA_SIZE] = core_req_byteen_in_sel;
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end
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assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : mem_req_byteen_in_r;
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assign mem_req_tag_out = mem_req_valid_in ? MEM_TAG_OUT_WIDTH'(mem_req_tag_in_nc) : MEM_TAG_OUT_WIDTH'({core_req_nc_tid, req_addr_idx, core_req_tag_in_sel});
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end else begin
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assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : core_req_byteen_in_sel;
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assign mem_req_tag_out = mem_req_valid_in ? MEM_TAG_OUT_WIDTH'(mem_req_tag_in_nc) : MEM_TAG_OUT_WIDTH'({core_req_nc_tid, core_req_tag_in_sel});
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end
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end else begin
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`UNUSED_VAR (core_req_nc_tid)
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assign mem_req_rw_out = mem_req_valid_in ? mem_req_rw_in : core_req_rw_in;
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assign mem_req_addr_out = mem_req_valid_in ? mem_req_addr_in : core_req_addr_in[0][D +: MEM_ADDR_WIDTH];
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for (genvar i = 0; i < P; ++i) begin
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assign mem_req_data_out[i * CORE_DATA_WIDTH +: CORE_DATA_WIDTH] = mem_req_valid_in ?
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mem_req_data_in[i * CORE_DATA_WIDTH +: CORE_DATA_WIDTH] : core_req_data_in;
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end
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if (D != 0) begin
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wire [D-1:0] req_addr_idx = core_req_addr_in[0][D-1:0];
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reg [MEM_DATA_SIZE-1:0] mem_req_byteen_in_r;
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always @(*) begin
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mem_req_byteen_in_r = 0;
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mem_req_byteen_in_r[req_addr_idx * CORE_DATA_SIZE +: CORE_DATA_SIZE] = core_req_byteen_in;
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end
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assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : mem_req_byteen_in_r;
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assign mem_req_tag_out = mem_req_valid_in ? MEM_TAG_OUT_WIDTH'(mem_req_tag_in_nc) : MEM_TAG_OUT_WIDTH'({req_addr_idx, core_req_tag_in});
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end else begin
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assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : core_req_byteen_in;
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assign mem_req_tag_out = mem_req_valid_in ? MEM_TAG_OUT_WIDTH'(mem_req_tag_in_nc) : MEM_TAG_OUT_WIDTH'(core_req_tag_in);
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end
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end
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// core response handling
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wire [NUM_RSP_TAGS-1:0][CORE_TAG_IN_WIDTH-1:0] core_rsp_tag_out_unqual;
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wire is_mem_rsp_nc = mem_rsp_valid_in && mem_rsp_tag_in[NC_TAG_BIT];
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for (genvar i = 0; i < NUM_RSP_TAGS; ++i) begin
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VX_bits_insert #(
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.N (CORE_TAG_OUT_WIDTH),
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.S (1),
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.POS (NC_TAG_BIT)
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) core_rsp_tag_insert (
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.data_in (core_rsp_tag_in[i]),
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.sel_in ('0),
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.data_out (core_rsp_tag_out_unqual[i])
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);
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end
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if (NUM_RSP_TAGS > 1) begin
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wire [CORE_REQ_TIDW-1:0] rsp_tid = mem_rsp_tag_in[(CORE_TAG_IN_WIDTH + D) +: CORE_REQ_TIDW];
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reg [NUM_REQS-1:0] rsp_nc_valid_r;
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always @(*) begin
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rsp_nc_valid_r = 0;
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rsp_nc_valid_r[rsp_tid] = is_mem_rsp_nc;
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end
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assign core_rsp_valid_out = core_rsp_valid_in | rsp_nc_valid_r;
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assign core_rsp_tmask_out = core_rsp_tmask_in;
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assign core_rsp_ready_in = core_rsp_ready_out;
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if (D != 0) begin
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wire [D-1:0] rsp_addr_idx = mem_rsp_tag_in[CORE_TAG_IN_WIDTH +: D];
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_rsp_data_out[i] = core_rsp_valid_in[i] ?
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core_rsp_data_in[i] : mem_rsp_data_in[rsp_addr_idx * CORE_DATA_WIDTH +: CORE_DATA_WIDTH];
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end
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end else begin
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_rsp_data_out[i] = core_rsp_valid_in[i] ? core_rsp_data_in[i] : mem_rsp_data_in;
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end
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end
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_rsp_tag_out[i] = core_rsp_valid_in[i] ? core_rsp_tag_out_unqual[i] : mem_rsp_tag_in[CORE_TAG_IN_WIDTH-1:0];
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end
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end else begin
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assign core_rsp_valid_out = core_rsp_valid_in || is_mem_rsp_nc;
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assign core_rsp_tag_out = core_rsp_valid_in ? core_rsp_tag_out_unqual : mem_rsp_tag_in[CORE_TAG_IN_WIDTH-1:0];
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assign core_rsp_ready_in = core_rsp_ready_out;
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if (NUM_REQS > 1) begin
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wire [CORE_REQ_TIDW-1:0] rsp_tid = mem_rsp_tag_in[(CORE_TAG_IN_WIDTH + D) +: CORE_REQ_TIDW];
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reg [NUM_REQS-1:0] core_rsp_tmask_in_r;
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always @(*) begin
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core_rsp_tmask_in_r = 0;
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core_rsp_tmask_in_r[rsp_tid] = 1;
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end
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assign core_rsp_tmask_out = core_rsp_valid_in ? core_rsp_tmask_in : core_rsp_tmask_in_r;
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end else begin
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assign core_rsp_tmask_out = core_rsp_tmask_in || is_mem_rsp_nc;
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end
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if (D != 0) begin
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wire [D-1:0] rsp_addr_idx = mem_rsp_tag_in[CORE_TAG_IN_WIDTH +: D];
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_rsp_data_out[i] = core_rsp_valid_in ?
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core_rsp_data_in[i] : mem_rsp_data_in[rsp_addr_idx * CORE_DATA_WIDTH +: CORE_DATA_WIDTH];
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end
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end else begin
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_rsp_data_out[i] = core_rsp_valid_in ? core_rsp_data_in[i] : mem_rsp_data_in;
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end
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end
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end
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// memory response handling
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assign mem_rsp_valid_out = mem_rsp_valid_in && ~mem_rsp_tag_in[NC_TAG_BIT];
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assign mem_rsp_data_out = mem_rsp_data_in;
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VX_bits_remove #(
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.N (MEM_TAG_IN_WIDTH+1),
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.S (1),
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.POS (NC_TAG_BIT)
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) mem_rsp_tag_remove (
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.data_in (mem_rsp_tag_in[(MEM_TAG_IN_WIDTH+1)-1:0]),
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.data_out (mem_rsp_tag_out)
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);
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if (NUM_RSP_TAGS > 1) begin
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wire [CORE_REQ_TIDW-1:0] rsp_tid = mem_rsp_tag_in[(CORE_TAG_IN_WIDTH + D) +: CORE_REQ_TIDW];
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assign mem_rsp_ready_in = is_mem_rsp_nc ? (~core_rsp_valid_in[rsp_tid] && core_rsp_ready_out[rsp_tid]) : mem_rsp_ready_out;
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end else begin
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assign mem_rsp_ready_in = is_mem_rsp_nc ? (~core_rsp_valid_in && core_rsp_ready_out) : mem_rsp_ready_out;
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end
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endmodule |