164 lines
3.6 KiB
Systemverilog
164 lines
3.6 KiB
Systemverilog
`ifndef VX_DEFINE
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`define VX_DEFINE
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`include "./VX_config.vh"
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// `define QUEUE_FORCE_MLAB 1
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// `define SYN 1
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// `define ASIC 1
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// `define SYN_FUNC 1
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`define LOG2UP(x) ((x > 1) ? $clog2(x) : 1)
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`define NUM_CORES_PER_CLUSTER (`NUM_CORES / `NUM_CLUSTERS)
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`define NW_BITS `LOG2UP(`NUM_WARPS)
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`define NT_BITS `LOG2UP(`NUM_THREADS)
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`define NC_BITS `LOG2UP(`NUM_CORES)
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`define R_INST 7'd51
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`define L_INST 7'd3
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`define ALU_INST 7'd19
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`define S_INST 7'd35
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`define B_INST 7'd99
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`define LUI_INST 7'd55
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`define AUIPC_INST 7'd23
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`define JAL_INST 7'd111
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`define JALR_INST 7'd103
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`define SYS_INST 7'd115
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`define GPGPU_INST 7'h6b
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`define WB_ALU 2'h1
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`define WB_MEM 2'h2
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`define WB_JAL 2'h3
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`define NO_WB 2'h0
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`define RS2_IMMED 1
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`define RS2_REG 0
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`define NO_MEM_READ 3'h7
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`define LB_MEM_READ 3'h0
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`define LH_MEM_READ 3'h1
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`define LW_MEM_READ 3'h2
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`define LBU_MEM_READ 3'h4
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`define LHU_MEM_READ 3'h5
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`define NO_MEM_WRITE 3'h7
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`define SB_MEM_WRITE 3'h0
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`define SH_MEM_WRITE 3'h1
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`define SW_MEM_WRITE 3'h2
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`define NO_BRANCH 3'h0
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`define BEQ 3'h1
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`define BNE 3'h2
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`define BLT 3'h3
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`define BGT 3'h4
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`define BLTU 3'h5
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`define BGTU 3'h6
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`define NO_ALU 5'd15
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`define ADD 5'd0
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`define SUB 5'd1
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`define SLLA 5'd2
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`define SLT 5'd3
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`define SLTU 5'd4
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`define XOR 5'd5
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`define SRL 5'd6
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`define SRA 5'd7
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`define OR 5'd8
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`define AND 5'd9
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`define SUBU 5'd10
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`define LUI_ALU 5'd11
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`define AUIPC_ALU 5'd12
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`define CSR_ALU_RW 5'd13
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`define CSR_ALU_RS 5'd14
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`define CSR_ALU_RC 5'd15
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`define MUL 5'd16
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`define MULH 5'd17
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`define MULHSU 5'd18
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`define MULHU 5'd19
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`define DIV 5'd20
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`define DIVU 5'd21
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`define REM 5'd22
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`define REMU 5'd23
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// WRITEBACK
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`define WB_ALU 2'h1
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`define WB_MEM 2'h2
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`define WB_JAL 2'h3
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`define NO_WB 2'h0
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// JAL
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`define JUMP 1'h1
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`define NO_JUMP 1'h0
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// STALLS
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`define STALL 1'h1
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`define NO_STALL 1'h0
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`define TAKEN 1'h1
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`define NOT_TAKEN 1'h0
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`define ZERO_REG 5'h0
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// ======================= Dcache Configurable Knobs ==========================
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// Function ID
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`define DFUNC_ID 0
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// Size of line inside a bank in bits
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`define DBANK_LINE_SIZE (`DBANK_LINE_SIZE_BYTES * 8)
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// Bank Number of words in a line
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`define DBANK_LINE_WORDS (`DBANK_LINE_SIZE_BYTES / `DWORD_SIZE_BYTES)
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// ======================= Icache Configurable Knobs ==========================
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// Function ID
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`define IFUNC_ID 1
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// Size of line inside a bank in bits
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`define IBANK_LINE_SIZE (`IBANK_LINE_SIZE_BYTES * 8)
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// Bank Number of words in a line
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`define IBANK_LINE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES)
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// ======================= SM Configurable Knobs ==============================
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// Function ID
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`define SFUNC_ID 2
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// Size of line inside a bank in bits
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`define SBANK_LINE_SIZE (`SBANK_LINE_SIZE_BYTES * 8)
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// Bank Number of words in a line
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`define SBANK_LINE_WORDS (`SBANK_LINE_SIZE_BYTES / `SWORD_SIZE_BYTES)
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// ======================= L2cache Configurable Knobs =========================
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// Function ID
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`define L2FUNC_ID 3
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// Size of line inside a bank in bits
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`define L2BANK_LINE_SIZE (`L2BANK_LINE_SIZE_BYTES * 8)
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// Bank Number of words in a line
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`define L2BANK_LINE_WORDS (`L2BANK_LINE_SIZE_BYTES / `L2WORD_SIZE_BYTES)
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// ======================= L3cache Configurable Knobs =========================
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// Function ID
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`define L3FUNC_ID 3
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// Size of line inside a bank in bits
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`define L3BANK_LINE_SIZE (`L3BANK_LINE_SIZE_BYTES * 8)
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// Bank Number of words in a line
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`define L3BANK_LINE_WORDS (`L3BANK_LINE_SIZE_BYTES / `L3WORD_SIZE_BYTES)
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// VX_DEFINE
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`endif
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