105 lines
3.1 KiB
Verilog
105 lines
3.1 KiB
Verilog
`include "VX_define.vh"
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module VX_fetch (
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input wire clk,
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input wire reset,
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VX_wstall_inter VX_wstall,
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VX_join_inter VX_join,
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input wire schedule_delay,
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input wire icache_stage_delay,
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input wire[`NW_BITS-1:0] icache_stage_wid,
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input wire[`NUM_THREADS-1:0] icache_stage_valids,
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output wire out_ebreak,
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VX_jal_response_inter VX_jal_rsp,
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VX_branch_response_inter VX_branch_rsp,
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VX_inst_meta_inter fe_inst_meta_fi,
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VX_warp_ctl_inter VX_warp_ctl
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);
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wire[`NUM_THREADS-1:0] thread_mask;
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wire[`NW_BITS-1:0] warp_num;
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wire[31:0] warp_pc;
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wire scheduled_warp;
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wire pipe_stall;
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// Only reason this is there is because there is a hidden assumption that decode is exactly after fetch
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// Locals
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assign pipe_stall = schedule_delay || icache_stage_delay;
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VX_warp_scheduler warp_scheduler(
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.clk (clk),
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.reset (reset),
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.stall (pipe_stall),
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.is_barrier (VX_warp_ctl.is_barrier),
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.barrier_id (VX_warp_ctl.barrier_id),
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.num_warps (VX_warp_ctl.num_warps),
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.barrier_warp_num (VX_warp_ctl.warp_num),
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// Wspawn
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.wspawn (VX_warp_ctl.wspawn),
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.wsapwn_pc (VX_warp_ctl.wspawn_pc),
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.wspawn_new_active(VX_warp_ctl.wspawn_new_active),
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// CTM
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.ctm (VX_warp_ctl.change_mask),
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.ctm_mask (VX_warp_ctl.thread_mask),
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.ctm_warp_num (VX_warp_ctl.warp_num),
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// WHALT
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.whalt (VX_warp_ctl.ebreak),
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.whalt_warp_num (VX_warp_ctl.warp_num),
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// Wstall
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.wstall (VX_wstall.wstall),
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.wstall_warp_num (VX_wstall.warp_num),
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// Lock/release Stuff
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.icache_stage_valids(icache_stage_valids),
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.icache_stage_wid (icache_stage_wid),
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// Join
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.is_join (VX_join.is_join),
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.join_warp_num (VX_join.join_warp_num),
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// Split
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.is_split (VX_warp_ctl.is_split),
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.dont_split (VX_warp_ctl.dont_split),
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.split_new_mask (VX_warp_ctl.split_new_mask),
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.split_later_mask (VX_warp_ctl.split_later_mask),
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.split_save_pc (VX_warp_ctl.split_save_pc),
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.split_warp_num (VX_warp_ctl.warp_num),
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// JAL
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.jal (VX_jal_rsp.jal),
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.jal_dest (VX_jal_rsp.jal_dest),
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.jal_warp_num (VX_jal_rsp.jal_warp_num),
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// Branch
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.branch_valid (VX_branch_rsp.valid_branch),
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.branch_dir (VX_branch_rsp.branch_dir),
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.branch_dest (VX_branch_rsp.branch_dest),
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.branch_warp_num (VX_branch_rsp.branch_warp_num),
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// Outputs
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.thread_mask (thread_mask),
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.warp_num (warp_num),
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.warp_pc (warp_pc),
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.out_ebreak (out_ebreak),
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.scheduled_warp (scheduled_warp)
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);
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assign fe_inst_meta_fi.warp_num = warp_num;
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assign fe_inst_meta_fi.valid = thread_mask;
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assign fe_inst_meta_fi.instruction = 32'h0;
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assign fe_inst_meta_fi.inst_pc = warp_pc;
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wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000ed8) && (warp_num == 0);
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wire end_mat_add = scheduled_warp && (warp_pc == 32'h80000fbc) && (warp_num == 0);
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endmodule |