132 lines
3.0 KiB
Verilog
132 lines
3.0 KiB
Verilog
`include "VX_define.vh"
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module VX_front_end (
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input wire clk,
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input wire reset,
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input wire schedule_delay,
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VX_warp_ctl_inter VX_warp_ctl,
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VX_gpu_dcache_res_inter VX_icache_rsp,
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VX_gpu_dcache_req_inter VX_icache_req,
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VX_jal_response_inter VX_jal_rsp,
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VX_branch_response_inter VX_branch_rsp,
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VX_frE_to_bckE_req_inter VX_bckE_req,
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output wire fetch_ebreak
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);
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VX_inst_meta_inter fe_inst_meta_fi();
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VX_inst_meta_inter fe_inst_meta_fi2();
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VX_inst_meta_inter fe_inst_meta_id();
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VX_frE_to_bckE_req_inter VX_frE_to_bckE_req();
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VX_inst_meta_inter fd_inst_meta_de();
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wire total_freeze = schedule_delay;
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wire icache_stage_delay;
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/* verilator lint_off UNUSED */
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// wire real_fetch_ebreak;
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/* verilator lint_on UNUSED */
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wire vortex_ebreak;
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wire terminate_sim;
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wire[`NW_BITS-1:0] icache_stage_wid;
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wire[`NUM_THREADS-1:0] icache_stage_valids;
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reg old_ebreak; // This should be eventually removed
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always @(posedge clk) begin
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if (reset) begin
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old_ebreak <= 0;
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end else begin
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old_ebreak <= old_ebreak || fetch_ebreak;
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end
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end
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assign fetch_ebreak = vortex_ebreak || terminate_sim || old_ebreak;
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VX_wstall_inter VX_wstall();
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VX_join_inter VX_join();
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VX_fetch vx_fetch(
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.clk (clk),
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.reset (reset),
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.icache_stage_wid (icache_stage_wid),
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.icache_stage_valids(icache_stage_valids),
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.VX_wstall (VX_wstall),
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.VX_join (VX_join),
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.schedule_delay (schedule_delay),
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.VX_jal_rsp (VX_jal_rsp),
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.VX_warp_ctl (VX_warp_ctl),
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.icache_stage_delay (icache_stage_delay),
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.VX_branch_rsp (VX_branch_rsp),
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.out_ebreak (vortex_ebreak), // fetch_ebreak
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.fe_inst_meta_fi (fe_inst_meta_fi)
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);
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wire freeze_fi_reg = total_freeze || icache_stage_delay;
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VX_f_d_reg vx_f_i_reg(
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.clk (clk),
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.reset (reset),
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.in_freeze (freeze_fi_reg),
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.fe_inst_meta_fd(fe_inst_meta_fi),
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.fd_inst_meta_de(fe_inst_meta_fi2)
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);
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VX_icache_stage VX_icache_stage(
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.clk (clk),
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.reset (reset),
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.total_freeze (total_freeze),
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.icache_stage_delay (icache_stage_delay),
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.icache_stage_valids(icache_stage_valids),
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.icache_stage_wid (icache_stage_wid),
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.fe_inst_meta_fi (fe_inst_meta_fi2),
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.fe_inst_meta_id (fe_inst_meta_id),
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.VX_icache_rsp (VX_icache_rsp),
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.VX_icache_req (VX_icache_req)
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);
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VX_i_d_reg vx_i_d_reg(
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.clk (clk),
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.reset (reset),
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.in_freeze (total_freeze),
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.fe_inst_meta_fd(fe_inst_meta_id),
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.fd_inst_meta_de(fd_inst_meta_de)
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);
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VX_decode vx_decode(
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.fd_inst_meta_de (fd_inst_meta_de),
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.VX_frE_to_bckE_req(VX_frE_to_bckE_req),
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.VX_wstall (VX_wstall),
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.VX_join (VX_join),
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.terminate_sim (terminate_sim)
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);
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wire no_br_stall = 0;
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VX_d_e_reg vx_d_e_reg(
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.clk (clk),
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.reset (reset),
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.in_branch_stall(no_br_stall),
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.in_freeze (total_freeze),
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.VX_frE_to_bckE_req(VX_frE_to_bckE_req),
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.VX_bckE_req (VX_bckE_req)
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);
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endmodule
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