87 lines
2.0 KiB
Verilog
87 lines
2.0 KiB
Verilog
`include "VX_define.vh"
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module VX_warp (
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input wire clk,
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input wire reset,
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input wire stall,
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input wire remove,
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input wire[`NUM_THREADS-1:0] in_thread_mask,
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input wire in_change_mask,
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input wire in_jal,
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input wire[31:0] in_jal_dest,
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input wire in_branch_dir,
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input wire[31:0] in_branch_dest,
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input wire in_wspawn,
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input wire[31:0] in_wspawn_pc,
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output wire[31:0] out_PC,
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output wire[`NUM_THREADS-1:0] out_valid
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);
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reg[31:0] real_PC;
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logic [31:0] temp_PC;
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logic [31:0] use_PC;
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reg[`NUM_THREADS-1:0] valid;
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reg[`NUM_THREADS-1:0] valid_zero;
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integer ini_cur_th = 0;
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initial begin
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real_PC = 0;
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for (ini_cur_th = 1; ini_cur_th < `NUM_THREADS; ini_cur_th=ini_cur_th+1) begin
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valid[ini_cur_th] = 0; // Thread 1 active
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valid_zero[ini_cur_th] = 0;
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end
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valid[0] = 1;
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valid_zero[0] = 0;
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end
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always @(posedge clk, posedge reset) begin
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if (remove) begin
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valid <= valid_zero;
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end else if (in_change_mask) begin
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valid <= in_thread_mask;
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end
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end
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genvar out_cur_th;
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generate
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for (out_cur_th = 0; out_cur_th < `NUM_THREADS; out_cur_th = out_cur_th+1) begin : out_valid_assign
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assign out_valid[out_cur_th] = in_change_mask ? in_thread_mask[out_cur_th] : stall ? 1'b0 : valid[out_cur_th];
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end
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endgenerate
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always @(*) begin
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if (in_jal == 1'b1) begin
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temp_PC = in_jal_dest;
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// $display("LINKING TO %h", temp_PC);
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end else if (in_branch_dir == 1'b1) begin
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temp_PC = in_branch_dest;
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end else begin
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temp_PC = real_PC;
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end
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end
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assign use_PC = temp_PC;
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assign out_PC = temp_PC;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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real_PC <= 0;
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end else if (in_wspawn == 1'b1) begin
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// $display("Inside warp ***** Spawn @ %H",in_wspawn_pc);
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real_PC <= in_wspawn_pc;
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end else if (!stall) begin
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real_PC <= use_PC + 32'h4;
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end else begin
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real_PC <= use_PC;
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end
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end
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endmodule |