286 lines
14 KiB
Verilog
286 lines
14 KiB
Verilog
`include "VX_define.vh"
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`include "VX_cache_config.vh"
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module Vortex_Cluster
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#(
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parameter CLUSTER_ID = 0
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) (
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// Clock
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input wire clk,
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input wire reset,
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// IO
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output wire[`NUM_CORES_PER_CLUSTER-1:0] io_valid,
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output wire[`NUM_CORES_PER_CLUSTER-1:0][31:0] io_data,
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// DRAM Req
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output wire out_dram_req,
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output wire out_dram_req_write,
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output wire out_dram_req_read,
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output wire [31:0] out_dram_req_addr,
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output wire [31:0] out_dram_req_size,
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output wire [31:0] out_dram_req_data[`DBANK_LINE_WORDS-1:0],
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output wire [31:0] out_dram_expected_lat,
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input wire out_dram_req_delay,
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// DRAM Res
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output wire out_dram_fill_accept,
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input wire out_dram_fill_rsp,
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input wire [31:0] out_dram_fill_rsp_addr,
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input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_WORDS-1:0],
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// LLC Snooping
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input wire llc_snp_req,
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input wire[31:0] llc_snp_req_addr,
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output wire llc_snp_req_delay,
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output wire out_ebreak
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);
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// DRAM Dcache Req
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wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_req;
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wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_req_write;
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wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_req_read;
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wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_addr;
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wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_size;
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wire[`NUM_CORES_PER_CLUSTER-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_req_data;
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wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_expected_lat;
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// DRAM Dcache Res
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wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_fill_accept;
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wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_fill_rsp;
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wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_fill_rsp_addr;
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wire[`NUM_CORES_PER_CLUSTER-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_fill_rsp_data;
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// DRAM Icache Req
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wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_req;
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wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_write;
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wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_read;
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wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_addr;
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wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_size;
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wire[`NUM_CORES_PER_CLUSTER-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_req_data;
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wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_expected_lat;
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// DRAM Icache Res
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wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_accept;
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wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_rsp;
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wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_fill_rsp_addr;
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wire[`NUM_CORES_PER_CLUSTER-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_fill_rsp_data;
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// Out ebreak
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wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_out_ebreak;
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wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_io_valid;
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wire[`NUM_CORES_PER_CLUSTER-1:0][31:0] per_core_io_data;
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wire l2c_core_accept;
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wire snp_fwd;
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wire[31:0] snp_fwd_addr;
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wire[`NUM_CORES_PER_CLUSTER-1:0] snp_fwd_delay;
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assign out_ebreak = (&per_core_out_ebreak);
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genvar curr_core;
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generate
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for (curr_core = 0; curr_core < `NUM_CORES_PER_CLUSTER; curr_core=curr_core+1) begin
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wire [`IBANK_LINE_WORDS-1:0][31:0] curr_core_I_dram_req_data;
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wire [`DBANK_LINE_WORDS-1:0][31:0] curr_core_dram_req_data ;
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assign io_valid[curr_core] = per_core_io_valid[curr_core];
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assign io_data [curr_core] = per_core_io_data [curr_core];
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Vortex #(
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.CORE_ID(curr_core + (CLUSTER_ID * `NUM_CORES_PER_CLUSTER))
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) vortex_core(
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.clk (clk),
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.reset (reset),
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.io_valid (per_core_io_valid [curr_core]),
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.io_data (per_core_io_data [curr_core]),
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.dram_req (per_core_dram_req [curr_core]),
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.dram_req_write (per_core_dram_req_write [curr_core]),
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.dram_req_read (per_core_dram_req_read [curr_core]),
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.dram_req_addr (per_core_dram_req_addr [curr_core]),
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.dram_req_size (per_core_dram_req_size [curr_core]),
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.dram_req_data (curr_core_dram_req_data ),
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.dram_expected_lat (per_core_dram_expected_lat [curr_core]),
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.dram_fill_accept (per_core_dram_fill_accept [curr_core]),
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.dram_fill_rsp (per_core_dram_fill_rsp [curr_core]),
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.dram_fill_rsp_addr (per_core_dram_fill_rsp_addr [curr_core]),
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.dram_fill_rsp_data (per_core_dram_fill_rsp_data [curr_core]),
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.I_dram_req (per_core_I_dram_req [curr_core]),
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.I_dram_req_write (per_core_I_dram_req_write [curr_core]),
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.I_dram_req_read (per_core_I_dram_req_read [curr_core]),
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.I_dram_req_addr (per_core_I_dram_req_addr [curr_core]),
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.I_dram_req_size (per_core_I_dram_req_size [curr_core]),
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.I_dram_req_data (curr_core_I_dram_req_data ),
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.I_dram_expected_lat (per_core_I_dram_expected_lat [curr_core]),
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.I_dram_fill_accept (per_core_I_dram_fill_accept [curr_core]),
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.I_dram_fill_rsp (per_core_I_dram_fill_rsp [curr_core]),
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.I_dram_fill_rsp_addr (per_core_I_dram_fill_rsp_addr[curr_core]),
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.I_dram_fill_rsp_data (per_core_I_dram_fill_rsp_data[curr_core]),
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.dram_req_delay (l2c_core_accept ),
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.out_ebreak (per_core_out_ebreak [curr_core]),
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.snp_req (snp_fwd),
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.snp_req_addr (snp_fwd_addr),
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.snp_req_delay (snp_fwd_delay[curr_core]),
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.I_snp_req (0),
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.I_snp_req_addr (),
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.I_snp_req_delay ()
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);
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assign per_core_dram_req_data [curr_core] = curr_core_dram_req_data;
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assign per_core_I_dram_req_data[curr_core] = curr_core_I_dram_req_data;
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end
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endgenerate
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//////////////////// L2 Cache ////////////////////
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wire[`L2NUMBER_REQUESTS-1:0] l2c_core_req;
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wire[`L2NUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_write;
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wire[`L2NUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_read;
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wire[`L2NUMBER_REQUESTS-1:0][31:0] l2c_core_req_addr;
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wire[`L2NUMBER_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l2c_core_req_data;
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wire[`L2NUMBER_REQUESTS-1:0][1:0] l2c_core_req_wb;
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wire[`L2NUMBER_REQUESTS-1:0] l2c_core_no_wb_slot;
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wire[`L2NUMBER_REQUESTS-1:0] l2c_wb;
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wire[`L2NUMBER_REQUESTS-1:0] [31:0] l2c_wb_addr;
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wire[`L2NUMBER_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l2c_wb_data;
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wire[`DBANK_LINE_WORDS-1:0][31:0] dram_req_data_port;
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wire[`DBANK_LINE_WORDS-1:0][31:0] dram_fill_rsp_data_port;
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genvar llb_index;
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generate
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for (llb_index = 0; llb_index < `DBANK_LINE_WORDS; llb_index=llb_index+1) begin
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assign out_dram_req_data [llb_index] = dram_req_data_port[llb_index];
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assign dram_fill_rsp_data_port[llb_index] = out_dram_fill_rsp_data[llb_index];
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end
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endgenerate
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genvar l2c_curr_core;
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generate
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for (l2c_curr_core = 0; l2c_curr_core < `L2NUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin
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// Core Request
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assign l2c_core_req [l2c_curr_core] = per_core_dram_req [(l2c_curr_core/2)];
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assign l2c_core_req [l2c_curr_core+1] = per_core_I_dram_req[(l2c_curr_core/2)];
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assign l2c_core_req_mem_write [l2c_curr_core] = per_core_dram_req_write[(l2c_curr_core/2)] ? `SW_MEM_WRITE : `NO_MEM_WRITE;
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assign l2c_core_req_mem_write [l2c_curr_core+1] = `NO_MEM_WRITE; // I caches don't write
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assign l2c_core_req_mem_read [l2c_curr_core] = per_core_dram_req_read[(l2c_curr_core/2)] ? `LW_MEM_READ : `NO_MEM_READ;
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assign l2c_core_req_mem_read [l2c_curr_core+1] = `LW_MEM_READ; // I caches don't write
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assign l2c_core_req_wb [l2c_curr_core] = per_core_dram_req_read[(l2c_curr_core/2)] ? 1 : 0;
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assign l2c_core_req_wb [l2c_curr_core+1] = 1; // I caches don't write
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assign l2c_core_req_addr [l2c_curr_core] = per_core_dram_req_addr [(l2c_curr_core/2)];
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assign l2c_core_req_addr [l2c_curr_core+1] = per_core_I_dram_req_addr[(l2c_curr_core/2)];
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assign l2c_core_req_data [l2c_curr_core] = per_core_dram_req_data [(l2c_curr_core/2)];
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assign l2c_core_req_data [l2c_curr_core+1] = per_core_I_dram_req_data[(l2c_curr_core/2)];
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// Core can't accept Response
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assign l2c_core_no_wb_slot [l2c_curr_core] = ~per_core_dram_fill_accept [(l2c_curr_core/2)];
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assign l2c_core_no_wb_slot [l2c_curr_core+1] = ~per_core_I_dram_fill_accept[(l2c_curr_core/2)];
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// Cache Fill Response
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assign per_core_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core];
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assign per_core_I_dram_fill_rsp [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core+1];
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assign per_core_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core];
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assign per_core_I_dram_fill_rsp_data[(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core+1];
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assign per_core_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core];
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assign per_core_I_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1];
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end
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endgenerate
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wire dram_snp_full;
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wire dram_req_because_of_wb;
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VX_cache #(
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.CACHE_SIZE_BYTES (`L2CACHE_SIZE_BYTES),
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.BANK_LINE_SIZE_BYTES (`L2BANK_LINE_SIZE_BYTES),
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.NUMBER_BANKS (`L2NUMBER_BANKS),
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.WORD_SIZE_BYTES (`L2WORD_SIZE_BYTES),
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.NUMBER_REQUESTS (`L2NUMBER_REQUESTS),
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.STAGE_1_CYCLES (`L2STAGE_1_CYCLES),
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.FUNC_ID (`L2FUNC_ID),
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.REQQ_SIZE (`L2REQQ_SIZE),
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.MRVQ_SIZE (`L2MRVQ_SIZE),
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.DFPQ_SIZE (`L2DFPQ_SIZE),
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.SNRQ_SIZE (`L2SNRQ_SIZE),
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.CWBQ_SIZE (`L2CWBQ_SIZE),
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.DWBQ_SIZE (`L2DWBQ_SIZE),
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.DFQQ_SIZE (`L2DFQQ_SIZE),
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.LLVQ_SIZE (`L2LLVQ_SIZE),
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.FFSQ_SIZE (`L2FFSQ_SIZE),
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.PRFQ_SIZE (`L2PRFQ_SIZE),
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.PRFQ_STRIDE (`L2PRFQ_STRIDE),
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.FILL_INVALIDAOR_SIZE (`L2FILL_INVALIDAOR_SIZE),
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.SIMULATED_DRAM_LATENCY_CYCLES(`L2SIMULATED_DRAM_LATENCY_CYCLES)
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) gpu_l2cache (
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.clk (clk),
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.reset (reset),
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// Core Req (DRAM Fills/WB) To L2 Request
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.core_req_valid (l2c_core_req),
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.core_req_addr (l2c_core_req_addr),
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.core_req_writedata({l2c_core_req_data}),
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.core_req_mem_read (l2c_core_req_mem_read),
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.core_req_mem_write(l2c_core_req_mem_write),
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.core_req_rd (0),
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.core_req_wb (l2c_core_req_wb),
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.core_req_warp_num (0),
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.core_req_pc (0),
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// L2 can't accept Core Request
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.delay_req (l2c_core_accept),
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// Core can't accept L2 Request
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.core_no_wb_slot (|l2c_core_no_wb_slot),
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// Core Writeback
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.core_wb_valid (l2c_wb),
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.core_wb_req_rd (),
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.core_wb_req_wb (),
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.core_wb_warp_num (),
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.core_wb_readdata ({l2c_wb_data}),
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.core_wb_address (l2c_wb_addr),
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.core_wb_pc (),
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// L2 Cache DRAM Fill response
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.dram_fill_rsp (out_dram_fill_rsp),
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.dram_fill_rsp_addr(out_dram_fill_rsp_addr),
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.dram_fill_rsp_data({dram_fill_rsp_data_port}),
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// L2 Cache can't accept Fill Response
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.dram_fill_accept (out_dram_fill_accept),
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// L2 Cache DRAM Fill Request
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.dram_req (out_dram_req),
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.dram_req_write (out_dram_req_write),
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.dram_req_read (out_dram_req_read),
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.dram_req_addr (out_dram_req_addr),
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.dram_req_size (out_dram_req_size),
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.dram_req_data ({dram_req_data_port}),
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.dram_req_delay (out_dram_req_delay),
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// Snoop Response
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.dram_req_because_of_wb(dram_req_because_of_wb),
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.dram_snp_full (dram_snp_full),
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// Snoop Request
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.snp_req (llc_snp_req),
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.snp_req_addr (llc_snp_req_addr),
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.snp_req_delay (llc_snp_req_delay),
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.snp_fwd (snp_fwd),
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.snp_fwd_addr (snp_fwd_addr),
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.snp_fwd_delay (|snp_fwd_delay)
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);
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endmodule |