293 lines
14 KiB
Verilog
293 lines
14 KiB
Verilog
`include "VX_define.vh"
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`include "VX_cache_config.vh"
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module Vortex_Socket (
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// Clock
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input wire clk,
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input wire reset,
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// IO
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output wire io_valid[`NUM_CORES-1:0],
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output wire[31:0] io_data [`NUM_CORES-1:0],
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output wire[31:0] number_cores,
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// DRAM Req
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output wire out_dram_req,
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output wire out_dram_req_write,
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output wire out_dram_req_read,
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output wire [31:0] out_dram_req_addr,
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output wire [31:0] out_dram_req_size,
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output wire [31:0] out_dram_req_data[`DBANK_LINE_WORDS-1:0],
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output wire [31:0] out_dram_expected_lat,
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input wire out_dram_req_delay,
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// DRAM Res
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output wire out_dram_fill_accept,
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input wire out_dram_fill_rsp,
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input wire [31:0] out_dram_fill_rsp_addr,
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input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_WORDS-1:0],
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// LLC Snooping
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input wire llc_snp_req,
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input wire[31:0] llc_snp_req_addr,
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output wire llc_snp_req_delay,
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output wire out_ebreak
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);
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assign number_cores = `NUM_CORES;
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if (`NUM_CLUSTERS == 1) begin
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wire[`NUM_CORES-1:0] cluster_io_valid;
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wire[`NUM_CORES-1:0][31:0] cluster_io_data;
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genvar curr_c;
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for (curr_c = 0; curr_c < `NUM_CORES; curr_c=curr_c+1) begin
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assign io_valid[curr_c] = cluster_io_valid[curr_c];
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assign io_data [curr_c] = cluster_io_data [curr_c];
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end
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Vortex_Cluster #(.CLUSTER_ID(0)) Vortex_Cluster(
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.clk (clk),
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.reset (reset),
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.io_valid (cluster_io_valid),
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.io_data (cluster_io_data),
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.out_dram_req (out_dram_req),
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.out_dram_req_write (out_dram_req_write),
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.out_dram_req_read (out_dram_req_read),
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.out_dram_req_addr (out_dram_req_addr),
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.out_dram_req_size (out_dram_req_size),
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.out_dram_req_data (out_dram_req_data),
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.out_dram_expected_lat (out_dram_expected_lat),
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.out_dram_req_delay (out_dram_req_delay),
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.out_dram_fill_accept (out_dram_fill_accept),
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.out_dram_fill_rsp (out_dram_fill_rsp),
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.out_dram_fill_rsp_addr(out_dram_fill_rsp_addr),
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.out_dram_fill_rsp_data(out_dram_fill_rsp_data),
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.llc_snp_req (llc_snp_req),
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.llc_snp_req_addr (llc_snp_req_addr),
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.llc_snp_req_delay (llc_snp_req_delay),
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.out_ebreak (out_ebreak)
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);
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end else begin
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wire snp_fwd;
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wire[31:0] snp_fwd_addr;
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wire[`NUM_CLUSTERS-1:0] snp_fwd_delay;
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wire[`NUM_CLUSTERS-1:0] per_cluster_out_ebreak;
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assign out_ebreak = (&per_cluster_out_ebreak);
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// // DRAM Dcache Req
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req;
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_write;
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_read;
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wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_req_addr;
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wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_req_size;
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wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_expected_lat;
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wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_req_data;
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wire[31:0] per_cluster_dram_req_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0];
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wire l3c_core_accept;
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// // DRAM Dcache Res
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_fill_accept;
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wire[`NUM_CLUSTERS-1:0] per_cluster_dram_fill_rsp;
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wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_fill_rsp_addr;
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wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_fill_rsp_data;
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wire[31:0] per_cluster_dram_fill_rsp_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0];
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wire[`NUM_CLUSTERS-1:0][`NUM_CORES_PER_CLUSTER-1:0] per_cluster_io_valid;
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wire[`NUM_CLUSTERS-1:0][`NUM_CORES_PER_CLUSTER-1:0][31:0] per_cluster_io_data;
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genvar curr_c, curr_cc, curr_word;
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for (curr_c = 0; curr_c < `NUM_CLUSTERS; curr_c =curr_c+1) begin
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for (curr_cc = 0; curr_cc < `NUM_CORES_PER_CLUSTER; curr_cc=curr_cc+1) begin
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assign io_valid[curr_cc+(curr_c*`NUM_CORES_PER_CLUSTER)] = per_cluster_io_valid[curr_c][curr_cc];
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assign io_data [curr_cc+(curr_c*`NUM_CORES_PER_CLUSTER)] = per_cluster_io_data [curr_c][curr_cc];
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end
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for (curr_word = 0; curr_word < `DBANK_LINE_WORDS; curr_word = curr_word+1) begin
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assign per_cluster_dram_req_data [curr_c][curr_word] = per_cluster_dram_req_data_up [curr_c][curr_word];
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assign per_cluster_dram_fill_rsp_data_up[curr_c][curr_word] = per_cluster_dram_fill_rsp_data[curr_c][curr_word];
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end
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end
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genvar curr_cluster;
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for (curr_cluster = 0; curr_cluster < `NUM_CLUSTERS; curr_cluster=curr_cluster+1) begin
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Vortex_Cluster #(.CLUSTER_ID(curr_cluster)) Vortex_Cluster(
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.clk (clk),
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.reset (reset),
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.io_valid (per_cluster_io_valid [curr_cluster]),
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.io_data (per_cluster_io_data [curr_cluster]),
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.out_dram_req (per_cluster_dram_req [curr_cluster]),
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.out_dram_req_write (per_cluster_dram_req_write [curr_cluster]),
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.out_dram_req_read (per_cluster_dram_req_read [curr_cluster]),
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.out_dram_req_addr (per_cluster_dram_req_addr [curr_cluster]),
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.out_dram_req_size (per_cluster_dram_req_size [curr_cluster]),
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.out_dram_req_data (per_cluster_dram_req_data_up [curr_cluster]),
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.out_dram_expected_lat (per_cluster_dram_expected_lat [curr_cluster]),
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.out_dram_req_delay (l3c_core_accept),
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.out_dram_fill_accept (per_cluster_dram_fill_accept [curr_cluster]),
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.out_dram_fill_rsp (per_cluster_dram_fill_rsp [curr_cluster]),
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.out_dram_fill_rsp_addr(per_cluster_dram_fill_rsp_addr [curr_cluster]),
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.out_dram_fill_rsp_data(per_cluster_dram_fill_rsp_data_up[curr_cluster]),
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.llc_snp_req (snp_fwd),
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.llc_snp_req_addr (snp_fwd_addr),
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.llc_snp_req_delay (snp_fwd_delay[curr_cluster]),
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.out_ebreak (per_cluster_out_ebreak [curr_cluster])
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);
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end
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//////////////////// L3 Cache ////////////////////
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wire[`L3NUMBER_REQUESTS-1:0] l3c_core_req;
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wire[`L3NUMBER_REQUESTS-1:0][2:0] l3c_core_req_mem_write;
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wire[`L3NUMBER_REQUESTS-1:0][2:0] l3c_core_req_mem_read;
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wire[`L3NUMBER_REQUESTS-1:0][31:0] l3c_core_req_addr;
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wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l3c_core_req_data;
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wire[`L3NUMBER_REQUESTS-1:0][1:0] l3c_core_req_wb;
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wire[`L3NUMBER_REQUESTS-1:0] l3c_core_no_wb_slot;
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wire[`L3NUMBER_REQUESTS-1:0] l3c_wb;
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wire[`L3NUMBER_REQUESTS-1:0] [31:0] l3c_wb_addr;
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wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l3c_wb_data;
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wire[`DBANK_LINE_WORDS-1:0][31:0] dram_req_data_port;
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wire[`DBANK_LINE_WORDS-1:0][31:0] dram_fill_rsp_data_port;
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genvar llb_index;
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for (llb_index = 0; llb_index < `DBANK_LINE_WORDS; llb_index=llb_index+1) begin
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assign out_dram_req_data [llb_index] = dram_req_data_port[llb_index];
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assign dram_fill_rsp_data_port[llb_index] = out_dram_fill_rsp_data[llb_index];
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end
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//
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genvar l3c_curr_cluster;
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for (l3c_curr_cluster = 0; l3c_curr_cluster < `L3NUMBER_REQUESTS; l3c_curr_cluster=l3c_curr_cluster+1) begin
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// Core Request
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assign l3c_core_req [l3c_curr_cluster] = per_cluster_dram_req [l3c_curr_cluster];
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assign l3c_core_req_mem_write [l3c_curr_cluster] = per_cluster_dram_req_write[l3c_curr_cluster] ? `SW_MEM_WRITE : `NO_MEM_WRITE;
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assign l3c_core_req_mem_read [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? `LW_MEM_READ : `NO_MEM_READ;
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assign l3c_core_req_wb [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? 1 : 0;
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assign l3c_core_req_addr [l3c_curr_cluster] = per_cluster_dram_req_addr [l3c_curr_cluster];
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assign l3c_core_req_data [l3c_curr_cluster] = per_cluster_dram_req_data [l3c_curr_cluster];
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// Core can't accept Response
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assign l3c_core_no_wb_slot [l3c_curr_cluster] = ~per_cluster_dram_fill_accept[l3c_curr_cluster];
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// Cache Fill Response
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assign per_cluster_dram_fill_rsp [l3c_curr_cluster] = l3c_wb [l3c_curr_cluster];
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assign per_cluster_dram_fill_rsp_data[l3c_curr_cluster] = l3c_wb_data[l3c_curr_cluster];
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assign per_cluster_dram_fill_rsp_addr[l3c_curr_cluster] = l3c_wb_addr[l3c_curr_cluster];
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end
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wire dram_snp_full;
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wire dram_req_because_of_wb;
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VX_cache #(
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.CACHE_SIZE_BYTES (`L3CACHE_SIZE_BYTES),
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.BANK_LINE_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES),
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.NUMBER_BANKS (`L3NUMBER_BANKS),
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.WORD_SIZE_BYTES (`L3WORD_SIZE_BYTES),
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.NUMBER_REQUESTS (`L3NUMBER_REQUESTS),
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.STAGE_1_CYCLES (`L3STAGE_1_CYCLES),
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.FUNC_ID (`L2FUNC_ID),
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.REQQ_SIZE (`L3REQQ_SIZE),
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.MRVQ_SIZE (`L3MRVQ_SIZE),
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.DFPQ_SIZE (`L3DFPQ_SIZE),
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.SNRQ_SIZE (`L3SNRQ_SIZE),
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.CWBQ_SIZE (`L3CWBQ_SIZE),
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.DWBQ_SIZE (`L3DWBQ_SIZE),
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.DFQQ_SIZE (`L3DFQQ_SIZE),
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.LLVQ_SIZE (`L3LLVQ_SIZE),
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.FFSQ_SIZE (`L3FFSQ_SIZE),
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.PRFQ_SIZE (`L3PRFQ_SIZE),
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.PRFQ_STRIDE (`L3PRFQ_STRIDE),
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.FILL_INVALIDAOR_SIZE (`L3FILL_INVALIDAOR_SIZE),
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.SIMULATED_DRAM_LATENCY_CYCLES(`L3SIMULATED_DRAM_LATENCY_CYCLES)
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) gpu_l3cache (
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.clk (clk),
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.reset (reset),
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// Core Req (DRAM Fills/WB) To L2 Request
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.core_req_valid (l3c_core_req),
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.core_req_addr (l3c_core_req_addr),
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.core_req_writedata({l3c_core_req_data}),
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.core_req_mem_read (l3c_core_req_mem_read),
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.core_req_mem_write(l3c_core_req_mem_write),
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.core_req_rd (0),
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.core_req_wb (l3c_core_req_wb),
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.core_req_warp_num (0),
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.core_req_pc (0),
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// L2 can't accept Core Request
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.delay_req (l3c_core_accept),
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// Core can't accept L2 Request
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.core_no_wb_slot (|l3c_core_no_wb_slot),
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// Core Writeback
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.core_wb_valid (l3c_wb),
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.core_wb_req_rd (),
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.core_wb_req_wb (),
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.core_wb_warp_num (),
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.core_wb_readdata ({l3c_wb_data}),
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.core_wb_address (l3c_wb_addr),
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.core_wb_pc (),
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// L2 Cache DRAM Fill response
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.dram_fill_rsp (out_dram_fill_rsp),
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.dram_fill_rsp_addr(out_dram_fill_rsp_addr),
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.dram_fill_rsp_data({dram_fill_rsp_data_port}),
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// L2 Cache can't accept Fill Response
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.dram_fill_accept (out_dram_fill_accept),
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// L2 Cache DRAM Fill Request
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.dram_req (out_dram_req),
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.dram_req_write (out_dram_req_write),
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.dram_req_read (out_dram_req_read),
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.dram_req_addr (out_dram_req_addr),
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.dram_req_size (out_dram_req_size),
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.dram_req_data ({dram_req_data_port}),
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.dram_req_delay (out_dram_req_delay),
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// Snoop Response
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.dram_req_because_of_wb(dram_req_because_of_wb),
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.dram_snp_full (dram_snp_full),
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// Snoop Request
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.snp_req (llc_snp_req),
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.snp_req_addr (llc_snp_req_addr),
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.snp_req_delay (llc_snp_req_delay),
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// Snoop Forward
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.snp_fwd (snp_fwd),
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.snp_fwd_addr (snp_fwd_addr),
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.snp_fwd_delay (|snp_fwd_delay)
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);
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end
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endmodule |