254 lines
8.4 KiB
Verilog
254 lines
8.4 KiB
Verilog
// To Do: Change way_id_out to an internal register which holds when in between access and finished.
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// Also add a bit about wheter the "Way ID" is valid / being held or if it is just default
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// Also make sure all possible output states are transmitted back to the bank correctly
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`include "VX_define.vh"
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module VX_Cache_Bank
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#(
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parameter CACHE_SIZE = 4096, // Bytes
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parameter CACHE_WAYS = 1,
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parameter CACHE_BLOCK = 128, // Bytes
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parameter CACHE_BANKS = 8,
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parameter LOG_NUM_BANKS = 3,
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parameter NUM_REQ = 8,
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parameter LOG_NUM_REQ = 3,
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parameter NUM_IND = 8,
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parameter CACHE_WAY_INDEX = 1,
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parameter NUM_WORDS_PER_BLOCK = 4,
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parameter OFFSET_SIZE_START = 0,
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parameter OFFSET_SIZE_END = 1,
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parameter TAG_SIZE_START = 0,
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parameter TAG_SIZE_END = 16,
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parameter IND_SIZE_START = 0,
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parameter IND_SIZE_END = 7,
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parameter ADDR_TAG_START = 15,
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parameter ADDR_TAG_END = 31,
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parameter ADDR_OFFSET_START = 5,
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parameter ADDR_OFFSET_END = 6,
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parameter ADDR_IND_START = 7,
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parameter ADDR_IND_END = 14
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)
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(
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clk,
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rst,
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state,
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read_or_write, // Read = 0 | Write = 1
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i_p_mem_read,
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i_p_mem_write,
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valid_in,
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//write_from_mem,
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actual_index,
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o_tag,
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block_offset,
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writedata,
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fetched_writedata,
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byte_select,
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readdata,
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hit,
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//miss,
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eviction_wb, // Need to evict
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eviction_addr, // What's the eviction tag
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data_evicted,
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evicted_way
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);
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// localparam NUMBER_BANKS = `CACHE_BANKS;
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// localparam CACHE_BLOCK_PER_BANK = (`CACHE_BLOCK / `CACHE_BANKS);
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// localparam NUM_WORDS_PER_BLOCK = `CACHE_BLOCK / (`CACHE_BANKS*4);
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// localparam NUMBER_INDEXES = `NUM_IND;
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localparam CACHE_IDLE = 0; // Idle
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localparam SEND_MEM_REQ = 1; // Write back this block into memory
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localparam RECIV_MEM_RSP = 2;
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localparam BLOCK_NUM_BITS = `LOG2UP(CACHE_BLOCK);
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// Inputs
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input wire rst;
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input wire clk;
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input wire [3:0] state;
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//input wire write_from_mem;
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// Reading Data
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input wire[IND_SIZE_END:IND_SIZE_START] actual_index;
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input wire[TAG_SIZE_END:TAG_SIZE_START] o_tag; // When write_from_mem = 1, o_tag is the new tag
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input wire[OFFSET_SIZE_END:OFFSET_SIZE_START] block_offset;
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input wire[31:0] writedata;
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input wire valid_in;
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input wire read_or_write; // Specifies if it is a read or write operation
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input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] fetched_writedata;
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input wire[2:0] i_p_mem_read;
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input wire[2:0] i_p_mem_write;
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input wire[1:0] byte_select;
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input wire[CACHE_WAY_INDEX-1:0] evicted_way;
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// Outputs
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// Normal shit
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output wire[31:0] readdata;
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output wire hit;
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//output wire miss;
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// Eviction Data (Notice)
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output wire eviction_wb; // Need to evict
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output wire[31:0] eviction_addr; // What's the eviction tag
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// Eviction Data (Extraction)
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output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_evicted;
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wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use;
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wire[TAG_SIZE_END:TAG_SIZE_START] tag_use;
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wire[TAG_SIZE_END:TAG_SIZE_START] eviction_tag;
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wire valid_use;
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wire dirty_use;
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wire access;
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wire write_from_mem;
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wire miss; // -10/21
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wire[CACHE_WAY_INDEX-1:0] way_to_update;
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assign miss = (tag_use != o_tag) && valid_use && valid_in;
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assign data_evicted = data_use;
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// assign eviction_wb = miss && (dirty_use != 1'b0) && valid_use;
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assign eviction_wb = (dirty_use != 1'b0);
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assign eviction_tag = tag_use;
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assign access = (state == CACHE_IDLE) && valid_in;
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assign write_from_mem = (state == RECIV_MEM_RSP) && valid_in; // TODO
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assign hit = (access && (tag_use == o_tag) && valid_use);
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//assign eviction_addr = {eviction_tag, actual_index, block_offset, 5'b0}; // Fix with actual data
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assign eviction_addr = {eviction_tag, actual_index, {(BLOCK_NUM_BITS){1'b0}}}; // Fix with actual data
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wire lw = (i_p_mem_read == `LW_MEM_READ);
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wire lb = (i_p_mem_read == `LB_MEM_READ);
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wire lh = (i_p_mem_read == `LH_MEM_READ);
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wire lhu = (i_p_mem_read == `LHU_MEM_READ);
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wire lbu = (i_p_mem_read == `LBU_MEM_READ);
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wire sw = (i_p_mem_write == `SW_MEM_WRITE);
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wire sb = (i_p_mem_write == `SB_MEM_WRITE);
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wire sh = (i_p_mem_write == `SH_MEM_WRITE);
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wire b0 = (byte_select == 0);
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wire b1 = (byte_select == 1);
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wire b2 = (byte_select == 2);
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wire b3 = (byte_select == 3);
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wire[31:0] data_unQual = (b0 || lw) ? (data_use[block_offset] ) :
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b1 ? (data_use[block_offset] >> 8) :
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b2 ? (data_use[block_offset] >> 16) :
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(data_use[block_offset] >> 24);
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wire[31:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF);
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wire[31:0] lh_data = (data_unQual[15]) ? (data_unQual | 32'hFFFF0000) : (data_unQual & 32'hFFFF);
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wire[31:0] lbu_data = (data_unQual & 32'hFF);
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wire[31:0] lhu_data = (data_unQual & 32'hFFFF);
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wire[31:0] lw_data = (data_unQual);
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wire[31:0] sw_data = writedata;
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wire[31:0] sb_data = b1 ? {{16{1'b0}}, writedata[7:0], { 8{1'b0}}} :
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b2 ? {{ 8{1'b0}}, writedata[7:0], {16{1'b0}}} :
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b3 ? {{ 0{1'b0}}, writedata[7:0], {24{1'b0}}} :
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writedata;
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wire[31:0] sh_data = b2 ? {writedata[15:0], {16{1'b0}}} : writedata;
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wire[31:0] use_write_data = sb ? sb_data :
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sh ? sh_data :
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sw_data;
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wire[31:0] data_Qual = lb ? lb_data :
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lh ? lh_data :
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lhu ? lhu_data :
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lbu ? lbu_data :
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lw_data;
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assign readdata = (access) ? data_Qual : 32'b0; // Fix with actual data
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wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000)));
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wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
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wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we;
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wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write;
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genvar g;
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generate
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for (g = 0; g < NUM_WORDS_PER_BLOCK; g = g + 1) begin : write_enables
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wire normal_write = (read_or_write && ((access && (block_offset == g))) && !miss);
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assign we[g] = (write_from_mem) ? 4'b1111 :
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(normal_write && sw) ? 4'b1111 :
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(normal_write && sb) ? sb_mask :
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(normal_write && sh) ? sh_mask :
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4'b0000;
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// assign we[g] = (normal_write || (write_from_mem)) ? 1'b1 : 1'b0;
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assign data_write[g] = write_from_mem ? fetched_writedata[g] : use_write_data;
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assign way_to_update = evicted_way;
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end
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endgenerate
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VX_cache_data_per_index #(
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.CACHE_WAYS (CACHE_WAYS),
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.NUM_IND (NUM_IND),
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.CACHE_WAY_INDEX (CACHE_WAY_INDEX),
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.NUM_WORDS_PER_BLOCK(NUM_WORDS_PER_BLOCK),
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.TAG_SIZE_START (TAG_SIZE_START),
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.TAG_SIZE_END (TAG_SIZE_END),
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.IND_SIZE_START (IND_SIZE_START),
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.IND_SIZE_END (IND_SIZE_END)) data_structures(
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.clk (clk),
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.rst (rst),
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.valid_in (valid_in),
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.state (state),
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// Inputs
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.addr (actual_index),
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.we (we),
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.evict (write_from_mem),
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.data_write (data_write),
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.tag_write (o_tag),
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.way_to_update(way_to_update),
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// Outputs
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.tag_use (tag_use),
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.data_use (data_use),
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.valid_use (valid_use),
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.dirty_use (dirty_use)
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);
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endmodule
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