31 lines
746 B
Verilog
31 lines
746 B
Verilog
`include "VX_define.vh"
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module VX_cache_bank_valid
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#(
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parameter NUMBER_BANKS = 8,
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parameter LOG_NUM_BANKS = 3,
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parameter NUM_REQ = 1
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)
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(
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input wire [NUM_REQ-1:0] i_p_valid,
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input wire [NUM_REQ-1:0][31:0] i_p_addr,
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output reg [NUMBER_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks
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);
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generate
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integer t_id;
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always @(*) begin
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thread_track_banks = 0;
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for (t_id = 0; t_id < NUM_REQ; t_id = t_id + 1)
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begin
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if (NUMBER_BANKS != 1) begin
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thread_track_banks[i_p_addr[t_id][2+LOG_NUM_BANKS-1:2]][t_id] = i_p_valid[t_id];
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end else begin
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thread_track_banks[0][t_id] = i_p_valid[t_id];
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end
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end
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end
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endgenerate
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endmodule
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