58 lines
1.8 KiB
Verilog
58 lines
1.8 KiB
Verilog
`include "VX_define.vh"
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`include "VX_d_cache.v"
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module VX_d_cache_tb;
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parameter NUMBER_BANKS = 8;
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reg clk, reset, im_ready;
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reg [`NUM_THREADS-1:0] i_p_valid;
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reg [`NUM_THREADS-1:0][13:0] i_p_addr; // FIXME
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reg i_p_initial_request;
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reg [`NUM_THREADS-1:0][31:0] i_p_writedata;
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reg i_p_read_or_write; //, i_p_write;
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reg [`NUM_THREADS-1:0][31:0] o_p_readdata;
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reg [`NUM_THREADS-1:0] o_p_readdata_valid;
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reg o_p_waitrequest;
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reg [13:0] o_m_addr; // Only one address is sent out at a time to memory
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reg o_m_valid;
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reg [(NUMBER_BANKS * 32) - 1:0] o_m_writedata;
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reg o_m_read_or_write; //, o_m_write;
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reg [(NUMBER_BANKS * 32) - 1:0] i_m_readdata; // Read Data that is passed from the memory module back to the controller
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VX_d_cache d_cache(.clk(clk),
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.rst(reset),
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.i_p_initial_request(i_p_initial_request),
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.i_p_addr(i_p_addr),
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.i_p_writedata(i_p_writedata),
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.i_p_read_or_write(i_p_read_or_write), // 0 = Read | 1 = Write
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.i_p_valid(i_p_valid),
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.o_p_readdata(o_p_readdata),
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.o_p_readdata_valid(o_p_readdata_valid),
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.o_p_waitrequest(o_p_waitrequest), // 0 = all threads done | 1 = Still threads that need to
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.o_m_addr(o_m_addr),
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.o_m_writedata(o_m_writedata),
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.o_m_read_or_write(o_m_read_or_write), // 0 = Read | 1 = Write
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.o_m_valid(o_m_valid),
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.i_m_readdata(i_m_readdata),
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.i_m_ready(im_ready)
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//cnt_r,
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//cnt_w,
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//cnt_hit_r,
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//cnt_hit_w
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);
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initial
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begin
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clk = 0;
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reset = 0;
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end
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always
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#5 clk = ! clk;
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endmodule |