20 lines
272 B
Verilog
20 lines
272 B
Verilog
`include "../generic_cache/VX_cache_config.vh"
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`ifndef VX_GPU_SNP_REQ_RSP
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`define VX_GPU_SNP_REQ_RSP
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interface VX_gpu_snp_req_rsp
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();
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// Snoop request
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wire snp_req;
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wire[31:0] snp_req_addr;
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// Snoop Response
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wire snp_delay;
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endinterface
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`endif |