19 lines
355 B
Verilog
19 lines
355 B
Verilog
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`include "../VX_define.vh"
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`ifndef VX_ICACHE_REQ
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`define VX_ICACHE_REQ
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interface VX_icache_request_inter ();
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wire[31:0] pc_address;
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wire[2:0] out_cache_driver_in_mem_read;
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wire[2:0] out_cache_driver_in_mem_write;
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wire out_cache_driver_in_valid;
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wire[31:0] out_cache_driver_in_data;
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endinterface
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`endif |