36 lines
706 B
Verilog
36 lines
706 B
Verilog
`include "../VX_define.vh"
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// Converts in_valids to bank_valids
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module VX_bank_valids
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#(
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parameter NB = 4,
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parameter BITS_PER_BANK = 3
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)
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(
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input wire[`NUM_THREADS-1:0] in_valids,
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input wire[`NUM_THREADS-1:0][31:0] in_addr,
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output reg[NB:0][`NUM_THREADS-1:0] bank_valids
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);
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integer i, j;
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always@(*) begin
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for(j = 0; j <= NB; j = j+1 ) begin
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for(i = 0; i < `NUM_THREADS; i = i+1) begin
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if(in_valids[i]) begin
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if(in_addr[i][(2+BITS_PER_BANK-1):2] == j[BITS_PER_BANK-1:0]) begin
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bank_valids[j][i] = 1'b1;
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end
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else begin
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bank_valids[j][i] = 1'b0;
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end
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end
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else begin
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bank_valids[j][i] = 1'b0;
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end
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end
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end
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end
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endmodule |