40 lines
636 B
Verilog
40 lines
636 B
Verilog
module VX_generic_stack
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#(
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parameter WIDTH = 40,
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parameter DEPTH = 2
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)
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(
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input wire clk,
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input wire reset,
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input wire push,
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input wire pop,
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input wire[WIDTH - 1:0] d,
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output reg [WIDTH - 1:0] q,
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);
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reg [DEPTH - 1:0] ptr;
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reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1];
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always @(posedge clk) begin
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if (reset)
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ptr <= 0;
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else if (push)
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ptr <= ptr + 1;
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else if (pop)
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ptr <= ptr - 1;
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end
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always @(posedge clk) begin
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if (push) begin
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if(push)
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stack[ptr] <= q;
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end
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end
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always @(*) begin
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if (pop)
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q <= stack[ptr - 1];
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end
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endmodule |