175 lines
6.0 KiB
Verilog
175 lines
6.0 KiB
Verilog
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`include "VX_define.v"
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module VX_forwarding (
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// INFO FROM DECODE
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VX_forward_reqeust_inter VX_fwd_req_de,
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VX_forward_exe_inter VX_fwd_exe,
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VX_forward_mem_inter VX_fwd_mem,
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VX_forward_wb_inter VX_fwd_wb,
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VX_forward_response_inter VX_fwd_rsp,
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output wire out_fwd_stall
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);
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wire[4:0] in_decode_src1 = VX_fwd_req_de.src1;
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wire[4:0] in_decode_src2 = VX_fwd_req_de.src2;
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wire[`NW_M1:0] in_decode_warp_num = VX_fwd_req_de.warp_num;
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wire[4:0] in_execute_dest = VX_fwd_exe.dest;
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wire[1:0] in_execute_wb = VX_fwd_exe.wb;
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wire[`NT_M1:0][31:0] in_execute_alu_result = VX_fwd_exe.alu_result;
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wire[31:0] in_execute_PC_next = VX_fwd_exe.PC_next;
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wire[`NW_M1:0] in_execute_warp_num = VX_fwd_exe.warp_num;
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wire[4:0] in_memory_dest = VX_fwd_mem.dest;
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wire[1:0] in_memory_wb = VX_fwd_mem.wb;
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wire[`NT_M1:0][31:0] in_memory_alu_result = VX_fwd_mem.alu_result;
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wire[`NT_M1:0][31:0] in_memory_mem_data = VX_fwd_mem.mem_data;
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wire[31:0] in_memory_PC_next = VX_fwd_mem.PC_next;
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wire[`NW_M1:0] in_memory_warp_num = VX_fwd_mem.warp_num;
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wire[4:0] in_writeback_dest = VX_fwd_wb.dest;
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wire[1:0] in_writeback_wb = VX_fwd_wb.wb;
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wire[`NT_M1:0][31:0] in_writeback_alu_result = VX_fwd_wb.alu_result;
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wire[`NT_M1:0][31:0] in_writeback_mem_data = VX_fwd_wb.mem_data;
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wire[31:0] in_writeback_PC_next = VX_fwd_wb.PC_next;
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wire[`NW_M1:0] in_writeback_warp_num = VX_fwd_wb.warp_num;
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wire out_src1_fwd;
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wire out_src2_fwd;
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wire[`NT_M1:0][31:0] out_src1_fwd_data;
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wire[`NT_M1:0][31:0] out_src2_fwd_data;
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assign VX_fwd_rsp.src1_fwd = out_src1_fwd;
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assign VX_fwd_rsp.src2_fwd = out_src2_fwd;
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assign VX_fwd_rsp.src1_fwd_data = out_src1_fwd_data;
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assign VX_fwd_rsp.src2_fwd_data = out_src2_fwd_data;
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wire exe_mem_read;
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wire mem_mem_read;
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wire wb_mem_read ;
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wire exe_jal;
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wire mem_jal;
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wire wb_jal ;
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wire src1_exe_fwd;
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wire src1_mem_fwd;
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wire src1_wb_fwd;
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wire src2_exe_fwd;
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wire src2_mem_fwd;
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wire src2_wb_fwd;
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wire[`NT_M1:0][31:0] use_execute_PC_next;
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wire[`NT_M1:0][31:0] use_memory_PC_next;
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wire[`NT_M1:0][31:0] use_writeback_PC_next;
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genvar index;
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generate
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for (index=0; index < `NT; index=index+1)
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begin: gen_code_label
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assign use_execute_PC_next[index] = in_execute_PC_next;
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assign use_memory_PC_next[index] = in_memory_PC_next;
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assign use_writeback_PC_next[index] = in_writeback_PC_next;
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end
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endgenerate
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assign exe_mem_read = (in_execute_wb == `WB_MEM);
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assign mem_mem_read = (in_memory_wb == `WB_MEM);
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assign wb_mem_read = (in_writeback_wb == `WB_MEM);
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assign exe_jal = (in_execute_wb == `WB_JAL);
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assign mem_jal = (in_memory_wb == `WB_JAL);
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assign wb_jal = (in_writeback_wb == `WB_JAL);
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// SRC1
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assign src1_exe_fwd = ((in_decode_src1 == in_execute_dest) &&
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(in_decode_src1 != `ZERO_REG) &&
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(in_execute_wb != `NO_WB)) &&
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(in_decode_warp_num == in_execute_warp_num);
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assign src1_mem_fwd = ((in_decode_src1 == in_memory_dest) &&
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(in_decode_src1 != `ZERO_REG) &&
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(in_memory_wb != `NO_WB) &&
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(!src1_exe_fwd)) &&
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(in_decode_warp_num == in_memory_warp_num);
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assign src1_wb_fwd = ((in_decode_src1 == in_writeback_dest) &&
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(in_decode_src1 != `ZERO_REG) &&
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(in_writeback_wb != `NO_WB) &&
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(in_writeback_warp_num == in_decode_warp_num) &&
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(!src1_exe_fwd) &&
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(!src1_mem_fwd));
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assign out_src1_fwd = src1_exe_fwd || src1_mem_fwd || (src1_wb_fwd && 0);
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// SRC2
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assign src2_exe_fwd = ((in_decode_src2 == in_execute_dest) &&
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(in_decode_src2 != `ZERO_REG) &&
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(in_execute_wb != `NO_WB)) &&
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(in_decode_warp_num == in_execute_warp_num);
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assign src2_mem_fwd = ((in_decode_src2 == in_memory_dest) &&
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(in_decode_src2 != `ZERO_REG) &&
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(in_memory_wb != `NO_WB) &&
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(!src2_exe_fwd)) &&
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(in_decode_warp_num == in_memory_warp_num);
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assign src2_wb_fwd = ((in_decode_src2 == in_writeback_dest) &&
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(in_decode_src2 != `ZERO_REG) &&
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(in_writeback_wb != `NO_WB) &&
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(!src2_exe_fwd) &&
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(!src2_mem_fwd)) &&
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(in_writeback_warp_num == in_decode_warp_num);
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assign out_src2_fwd = src2_exe_fwd || src2_mem_fwd || (src2_wb_fwd && 0);
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wire exe_mem_read_stall = ((src1_exe_fwd || src2_exe_fwd) && exe_mem_read) ? `STALL : `NO_STALL;
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wire mem_mem_read_stall = ((src1_mem_fwd || src2_mem_fwd) && mem_mem_read) ? `STALL : `NO_STALL;
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assign out_fwd_stall = exe_mem_read_stall || mem_mem_read_stall;
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// always @(*) begin
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// if (out_fwd_stall) $display("FWD STALL");
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// end
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assign out_src1_fwd_data = src1_exe_fwd ? ((exe_jal) ? use_execute_PC_next : in_execute_alu_result) :
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(src1_mem_fwd) ? ((mem_jal) ? use_memory_PC_next : (mem_mem_read ? in_memory_mem_data : in_memory_alu_result)) :
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( src1_wb_fwd ) ? (wb_jal ? use_writeback_PC_next : (wb_mem_read ? in_writeback_mem_data : in_writeback_alu_result)) :
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in_execute_alu_result; // last one should be deadbeef
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assign out_src2_fwd_data = src2_exe_fwd ? ((exe_jal) ? use_execute_PC_next : in_execute_alu_result) :
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(src2_mem_fwd) ? ((mem_jal) ? use_memory_PC_next : (mem_mem_read ? in_memory_mem_data : in_memory_alu_result)) :
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( src2_wb_fwd ) ? (wb_jal ? use_writeback_PC_next : (wb_mem_read ? in_writeback_mem_data : in_writeback_alu_result)) :
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in_execute_alu_result; // last one should be deadbeef
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endmodule // VX_forwarding
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