d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
64 lines
1.7 KiB
Systemverilog
64 lines
1.7 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_scope_switch #(
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parameter N = 0
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) (
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input wire clk,
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input wire reset,
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input wire req_in,
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output wire req_out [N],
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input wire rsp_in [N],
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output wire rsp_out
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);
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if (N > 1) begin
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reg req_out_r [N];
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reg rsp_out_r;
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always @(posedge clk) begin
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if (reset) begin
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for (integer i = 0; i < N; ++i) begin
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req_out_r[i] <= 0;
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end
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rsp_out_r <= 0;
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end else begin
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for (integer i = 0; i < N; ++i) begin
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req_out_r[i] <= req_in;
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end
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rsp_out_r <= 0;
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for (integer i = 0; i < N; ++i) begin
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if (rsp_in[i])
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rsp_out_r <= 1;
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end
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end
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end
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assign req_out = req_out_r;
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assign rsp_out = rsp_out_r;
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end else begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign req_out[0] = req_in;
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assign rsp_out = rsp_in[0];
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end
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endmodule
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`TRACING_ON
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