123 lines
5.9 KiB
Verilog
123 lines
5.9 KiB
Verilog
`include "VX_define.vh"
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module VX_writeback #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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VX_exu_to_cmt_if alu_commit_if,
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VX_exu_to_cmt_if lsu_commit_if,
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VX_exu_to_cmt_if csr_commit_if,
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VX_exu_to_cmt_if mul_commit_if,
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VX_fpu_to_cmt_if fpu_commit_if,
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VX_exu_to_cmt_if gpu_commit_if,
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VX_cmt_to_issue_if cmt_to_issue_if,
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// outputs
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VX_wb_if writeback_if
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);
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reg [`NUM_THREADS-1:0][31:0] wb_data [`ISSUEQ_SIZE-1:0];
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reg [`NW_BITS-1:0] wb_warp_num [`ISSUEQ_SIZE-1:0];
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reg [`NUM_THREADS-1:0] wb_thread_mask [`ISSUEQ_SIZE-1:0];
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reg [31:0] wb_curr_PC [`ISSUEQ_SIZE-1:0];
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reg [`NR_BITS-1:0] wb_rd [`ISSUEQ_SIZE-1:0];
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reg wb_rd_is_fp [`ISSUEQ_SIZE-1:0];
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reg [`ISSUEQ_SIZE-1:0] wb_pending;
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wire [`ISTAG_BITS-1:0] wb_index;
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wire wb_valid, wb_valid_unqual;
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VX_priority_encoder #(
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.N(`ISSUEQ_SIZE)
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) free_slots_encoder (
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.data_in (wb_pending),
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.data_out (wb_index),
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.valid_out (wb_valid_unqual)
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);
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assign wb_valid = wb_valid_unqual && writeback_if.ready;
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always @(posedge clk) begin
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if (reset) begin
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wb_pending <= 0;
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end else begin
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if (alu_commit_if.valid) begin
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wb_data [alu_commit_if.issue_tag] <= alu_commit_if.data;
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wb_warp_num [alu_commit_if.issue_tag] <= cmt_to_issue_if.alu_data.warp_num;
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wb_thread_mask [alu_commit_if.issue_tag] <= cmt_to_issue_if.alu_data.thread_mask;
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wb_curr_PC [alu_commit_if.issue_tag] <= cmt_to_issue_if.alu_data.curr_PC;
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wb_rd [alu_commit_if.issue_tag] <= cmt_to_issue_if.alu_data.rd;
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wb_rd_is_fp [alu_commit_if.issue_tag] <= cmt_to_issue_if.alu_data.rd_is_fp;
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wb_pending [alu_commit_if.issue_tag] <= cmt_to_issue_if.alu_data.wb;
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end
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if (lsu_commit_if.valid) begin
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wb_data [lsu_commit_if.issue_tag] <= lsu_commit_if.data;
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wb_warp_num [lsu_commit_if.issue_tag] <= cmt_to_issue_if.lsu_data.warp_num;
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wb_thread_mask [lsu_commit_if.issue_tag] <= cmt_to_issue_if.lsu_data.thread_mask;
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wb_curr_PC [lsu_commit_if.issue_tag] <= cmt_to_issue_if.lsu_data.curr_PC;
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wb_rd [lsu_commit_if.issue_tag] <= cmt_to_issue_if.lsu_data.rd;
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wb_rd_is_fp [lsu_commit_if.issue_tag] <= cmt_to_issue_if.lsu_data.rd_is_fp;
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wb_pending [lsu_commit_if.issue_tag] <= cmt_to_issue_if.lsu_data.wb;
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end
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if (csr_commit_if.valid) begin
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wb_data [csr_commit_if.issue_tag] <= csr_commit_if.data;
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wb_warp_num [csr_commit_if.issue_tag] <= cmt_to_issue_if.csr_data.warp_num;
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wb_thread_mask [csr_commit_if.issue_tag] <= cmt_to_issue_if.csr_data.thread_mask;
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wb_curr_PC [csr_commit_if.issue_tag] <= cmt_to_issue_if.csr_data.curr_PC;
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wb_rd [csr_commit_if.issue_tag] <= cmt_to_issue_if.csr_data.rd;
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wb_rd_is_fp [csr_commit_if.issue_tag] <= cmt_to_issue_if.csr_data.rd_is_fp;
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wb_pending [csr_commit_if.issue_tag] <= cmt_to_issue_if.csr_data.wb;
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end
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if (mul_commit_if.valid) begin
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wb_data [mul_commit_if.issue_tag] <= mul_commit_if.data;
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wb_warp_num [mul_commit_if.issue_tag] <= cmt_to_issue_if.mul_data.warp_num;
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wb_thread_mask [mul_commit_if.issue_tag] <= cmt_to_issue_if.mul_data.thread_mask;
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wb_curr_PC [mul_commit_if.issue_tag] <= cmt_to_issue_if.mul_data.curr_PC;
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wb_rd [mul_commit_if.issue_tag] <= cmt_to_issue_if.mul_data.rd;
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wb_rd_is_fp [mul_commit_if.issue_tag] <= cmt_to_issue_if.mul_data.rd_is_fp;
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wb_pending [mul_commit_if.issue_tag] <= cmt_to_issue_if.mul_data.wb;
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end
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if (fpu_commit_if.valid) begin
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wb_data [fpu_commit_if.issue_tag] <= fpu_commit_if.data;
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wb_warp_num [fpu_commit_if.issue_tag] <= cmt_to_issue_if.fpu_data.warp_num;
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wb_thread_mask [fpu_commit_if.issue_tag] <= cmt_to_issue_if.fpu_data.thread_mask;
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wb_curr_PC [fpu_commit_if.issue_tag] <= cmt_to_issue_if.fpu_data.curr_PC;
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wb_rd [fpu_commit_if.issue_tag] <= cmt_to_issue_if.fpu_data.rd;
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wb_rd_is_fp [fpu_commit_if.issue_tag] <= cmt_to_issue_if.fpu_data.rd_is_fp;
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wb_pending [fpu_commit_if.issue_tag] <= cmt_to_issue_if.fpu_data.wb;
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end
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if (wb_valid) begin
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wb_pending [wb_index] <= 0;
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end
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end
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end
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// writeback request
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assign writeback_if.valid = wb_pending [wb_index];
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assign writeback_if.warp_num = wb_warp_num [wb_index];
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assign writeback_if.thread_mask = wb_thread_mask [wb_index];
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assign writeback_if.curr_PC = wb_curr_PC [wb_index];
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assign writeback_if.rd = wb_rd [wb_index];
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assign writeback_if.rd_is_fp = wb_rd_is_fp [wb_index];
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assign writeback_if.data = wb_data [wb_index];
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// commit back-pressure
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assign alu_commit_if.ready = 1'b1;
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assign lsu_commit_if.ready = 1'b1;
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assign csr_commit_if.ready = 1'b1;
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assign mul_commit_if.ready = 1'b1;
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assign fpu_commit_if.ready = 1'b1;
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assign gpu_commit_if.ready = 1'b1;
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// special workaround to get RISC-V tests Pass/Fail status
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reg [31:0] last_wb_value [`NUM_REGS-1:0] /* verilator public */;
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always @(posedge clk) begin
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if (writeback_if.valid) begin
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last_wb_value[writeback_if.rd] <= writeback_if.data[0];
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end
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end
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endmodule |