225 lines
7.4 KiB
Verilog
225 lines
7.4 KiB
Verilog
`include "VX_platform.vh"
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module VX_generic_queue #(
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parameter DATAW = 1,
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parameter SIZE = 2,
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parameter BUFFERED = 0,
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parameter ADDRW = $clog2(SIZE),
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parameter SIZEW = $clog2(SIZE+1)
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) (
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input wire clk,
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input wire reset,
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input wire push,
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input wire pop,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out,
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output wire empty,
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output wire full,
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output wire [SIZEW-1:0] size
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);
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`STATIC_ASSERT(`ISPOW2(SIZE), ("must be 0 or power of 2!"))
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always @(*) begin
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assert(!pop || !empty);
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assert(!push || !full);
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end
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if (SIZE == 1) begin // (SIZE == 1)
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reg [SIZEW-1:0] size_r;
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reg [DATAW-1:0] head_r;
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always @(posedge clk) begin
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if (reset) begin
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head_r <= 0;
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size_r <= 0;
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end else begin
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if (push && !pop) begin
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size_r <= 1;
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end else if (pop && !push) begin
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size_r <= 0;
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end
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if (push) begin
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head_r <= data_in;
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end
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end
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end
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assign data_out = head_r;
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assign empty = (size_r == 0);
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assign full = (size_r != 0);
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assign size = size_r;
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end else begin // (SIZE > 1)
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`ifdef QUARTUS
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scfifo scfifo_component (
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.clock (clk),
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.data (data_in),
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.rdreq (pop),
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.wrreq (push),
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.empty (empty),
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.full (full),
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.q (data_out),
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.sclr (reset),
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.usedw (),
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.aclr (),
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.almost_empty (),
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.almost_full (),
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.eccstatus ()
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);
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defparam
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scfifo_component.lpm_type = "scfifo",
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scfifo_component.intended_device_family = "Arria 10",
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scfifo_component.lpm_numwords = SIZE,
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scfifo_component.lpm_width = DATAW,
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scfifo_component.lpm_widthu = $clog2(SIZE),
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scfifo_component.lpm_showahead = "ON",
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scfifo_component.add_ram_output_register = (BUFFERED ? "ON" : "ON"),
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scfifo_component.use_eab = "ON";
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reg [SIZEW-1:0] size_r;
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always @(posedge clk) begin
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if (reset) begin
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size_r <= 0;
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end else begin
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if (push && !pop) begin
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size_r <= size_r + SIZEW'(1);
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end
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if (pop && !push) begin
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size_r <= size_r - SIZEW'(1);
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end
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end
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end
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assign size = size_r;
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`else
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`USE_FAST_BRAM reg [DATAW-1:0] data [SIZE-1:0];
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if (0 == BUFFERED) begin
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reg [SIZEW-1:0] size_r;
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reg [ADDRW:0] rd_ptr_r;
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reg [ADDRW:0] wr_ptr_r;
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wire [ADDRW-1:0] rd_ptr_a = rd_ptr_r[ADDRW-1:0];
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wire [ADDRW-1:0] wr_ptr_a = wr_ptr_r[ADDRW-1:0];
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always @(posedge clk) begin
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if (reset) begin
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rd_ptr_r <= 0;
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wr_ptr_r <= 0;
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size_r <= 0;
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end else begin
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if (push) begin
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wr_ptr_r <= wr_ptr_r + (ADDRW+1)'(1);
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if (!pop) begin
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size_r <= size_r + SIZEW'(1);
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end
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end
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if (pop) begin
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rd_ptr_r <= rd_ptr_r + (ADDRW+1)'(1);
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if (!push) begin
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size_r <= size_r - SIZEW'(1);
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end
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end
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end
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end
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always @(posedge clk) begin
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if (push) begin
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data[wr_ptr_a] <= data_in;
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end
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end
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assign data_out = data[rd_ptr_a];
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assign empty = (wr_ptr_r == rd_ptr_r);
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assign full = (wr_ptr_a == rd_ptr_a) && (wr_ptr_r[ADDRW] != rd_ptr_r[ADDRW]);
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assign size = size_r;
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end else begin
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reg [SIZEW-1:0] size_r;
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reg [DATAW-1:0] head_r;
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reg [DATAW-1:0] curr_r;
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reg [ADDRW-1:0] wr_ptr_r;
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reg [ADDRW-1:0] rd_ptr_r;
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reg [ADDRW-1:0] rd_ptr_next_r;
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reg empty_r;
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reg full_r;
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reg bypass_r;
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always @(posedge clk) begin
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if (reset) begin
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size_r <= 0;
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curr_r <= 0;
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wr_ptr_r <= 0;
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rd_ptr_r <= 0;
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rd_ptr_next_r <= 1;
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empty_r <= 1;
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full_r <= 0;
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end else begin
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if (push) begin
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wr_ptr_r <= wr_ptr_r + ADDRW'(1);
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if (!pop) begin
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empty_r <= 0;
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if (size_r == SIZEW'(SIZE-1)) begin
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full_r <= 1;
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end
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size_r <= size_r + SIZEW'(1);
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end
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end
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if (pop) begin
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rd_ptr_r <= rd_ptr_next_r;
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if (SIZE > 2) begin
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rd_ptr_next_r <= rd_ptr_r + ADDRW'(2);
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end else begin // (SIZE == 2);
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rd_ptr_next_r <= ~rd_ptr_next_r;
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end
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if (!push) begin
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if (size_r == SIZEW'(1)) begin
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assert(rd_ptr_next_r == wr_ptr_r);
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empty_r <= 1;
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end;
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full_r <= 0;
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size_r <= size_r - SIZEW'(1);
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end
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end
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bypass_r <= push && (empty_r || ((size_r == SIZEW'(1)) && pop));
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curr_r <= data_in;
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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head_r <= 0;
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end else begin
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if (push) begin
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data[wr_ptr_r] <= data_in;
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end
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head_r <= data[pop ? rd_ptr_next_r : rd_ptr_r];
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end
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end
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assign data_out = bypass_r ? curr_r : head_r;
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assign empty = empty_r;
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assign full = full_r;
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assign size = size_r;
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end
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`endif
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end
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endmodule
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