48 lines
1.3 KiB
Verilog
48 lines
1.3 KiB
Verilog
`include "VX_platform.vh"
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module VX_skid_buffer #(
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parameter DATAW = 1
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out,
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input wire ready_out,
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output wire valid_out
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);
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reg [DATAW-1:0] data_out_r;
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reg [DATAW-1:0] buffer;
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reg valid_out_r;
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reg use_buffer;
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always @(posedge clk) begin
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if (reset) begin
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data_out_r <= 0;
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buffer <= 0;
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use_buffer <= 0;
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valid_out_r <= 0;
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end else begin
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if (valid_in && ready_in && valid_out && !ready_out) begin
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assert(!use_buffer);
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use_buffer <= 1;
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end
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if (ready_out) begin
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use_buffer <= 0;
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end
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if (valid_in && ready_in) begin
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buffer <= data_in;
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end
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if (!valid_out || ready_out) begin
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valid_out_r <= valid_in || use_buffer;
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data_out_r <= use_buffer ? buffer : data_in;
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end
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end
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end
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assign ready_in = !use_buffer;
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assign valid_out = valid_out_r;
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assign data_out = data_out_r;
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endmodule |