190 lines
7.1 KiB
Verilog
190 lines
7.1 KiB
Verilog
`include "VX_cache_config.v"
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module VX_cache_req_queue
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#(
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// Size of cache in bytes
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parameter CACHE_SIZE_BYTES = 1024,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE_BYTES = 16,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUMBER_BANKS = 8,
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// Size of a word in bytes
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parameter WORD_SIZE_BYTES = 4,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUMBER_REQUESTS = 2,
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// Number of cycles to complete stage 1 (read from memory)
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parameter STAGE_1_CYCLES = 2,
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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parameter REQQ_SIZE = 8,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 8,
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// Dram Fill Rsp Queue Size
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parameter DFPQ_SIZE = 2,
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// Snoop Req Queue
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parameter SNRQ_SIZE = 8,
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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parameter CWBQ_SIZE = 8,
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// Dram Writeback Queue Size
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parameter DWBQ_SIZE = 4,
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// Dram Fill Req Queue Size
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parameter DFQQ_SIZE = 8,
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// Lower Level Cache Hit Queue Size
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parameter LLVQ_SIZE = 16,
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// Fill Invalidator Size {Fill invalidator must be active}
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parameter FILL_INVALIDAOR_SIZE = 16,
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// Dram knobs
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parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
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)
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(
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input wire clk,
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input wire reset,
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// Enqueue Data
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input wire reqq_push,
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input wire [NUMBER_REQUESTS-1:0] bank_valids,
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input wire [NUMBER_REQUESTS-1:0][31:0] bank_addr,
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input wire [NUMBER_REQUESTS-1:0][31:0] bank_writedata,
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input wire [4:0] bank_rd,
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input wire [1:0] bank_wb,
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input wire [`NW_M1:0] bank_warp_num,
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input wire [2:0] bank_mem_read,
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input wire [2:0] bank_mem_write,
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// Dequeue Data
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input wire reqq_pop,
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output wire reqq_req_st0,
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output wire [`vx_clog2(NUMBER_REQUESTS)-1:0] reqq_req_tid_st0,
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output wire [31:0] reqq_req_addr_st0,
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output wire [31:0] reqq_req_writedata_st0,
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output wire [4:0] reqq_req_rd_st0,
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output wire [1:0] reqq_req_wb_st0,
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output wire [`NW_M1:0] reqq_req_warp_num_st0,
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output wire [2:0] reqq_req_mem_read_st0,
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output wire [2:0] reqq_req_mem_write_st0,
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// State Data
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output wire reqq_empty,
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output wire reqq_full
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);
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wire [NUMBER_REQUESTS-1:0] out_per_valids;
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wire [NUMBER_REQUESTS-1:0][31:0] out_per_addr;
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wire [NUMBER_REQUESTS-1:0][31:0] out_per_writedata;
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wire [4:0] out_per_rd;
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wire [1:0] out_per_wb;
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wire [`NW_M1:0] out_per_warp_num;
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wire [2:0] out_per_mem_read;
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wire [2:0] out_per_mem_write;
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reg [NUMBER_REQUESTS-1:0] use_per_valids;
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reg [NUMBER_REQUESTS-1:0][31:0] use_per_addr;
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reg [NUMBER_REQUESTS-1:0][31:0] use_per_writedata;
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reg [4:0] use_per_rd;
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reg [1:0] use_per_wb;
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reg [`NW_M1:0] use_per_warp_num;
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reg [2:0] use_per_mem_read;
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reg [2:0] use_per_mem_write;
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wire [NUMBER_REQUESTS-1:0] qual_valids;
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wire [NUMBER_REQUESTS-1:0][31:0] qual_addr;
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wire [NUMBER_REQUESTS-1:0][31:0] qual_writedata;
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wire [4:0] qual_rd;
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wire [1:0] qual_wb;
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wire [`NW_M1:0] qual_warp_num;
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wire [2:0] qual_mem_read;
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wire [2:0] qual_mem_write;
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wire[NUMBER_REQUESTS-1:0] updated_valids;
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wire o_empty;
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wire use_empty = !(|use_per_valids);
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wire out_empty = !(|out_per_valids) || o_empty;
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wire push_qual = reqq_push && !reqq_full;
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wire pop_qual = reqq_pop && use_empty && !out_empty;
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VX_generic_queue_ll #(.DATAW( (NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(REQQ_SIZE)) reqq_queue(
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.clk (clk),
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.reset (reset),
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.push (push_qual),
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.in_data ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write}),
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.pop (pop_qual),
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.out_data({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write}),
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.empty (o_empty),
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.full (reqq_full)
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);
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wire[NUMBER_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUMBER_REQUESTS{~out_empty}};
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assign qual_valids = use_empty ? real_out_per_valids : out_empty ? 0 : use_per_valids;
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assign qual_addr = use_empty ? out_per_addr : use_per_addr;
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assign qual_writedata = use_empty ? out_per_writedata : use_per_writedata;
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assign qual_rd = use_empty ? out_per_rd : use_per_rd;
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assign qual_wb = use_empty ? out_per_wb : use_per_wb;
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assign qual_warp_num = use_empty ? out_per_warp_num : use_per_warp_num;
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assign qual_mem_read = use_empty ? out_per_mem_read : use_per_mem_read;
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assign qual_mem_write = use_empty ? out_per_mem_write : use_per_mem_write;
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wire[`vx_clog2(NUMBER_REQUESTS)-1:0] qual_request_index;
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wire qual_has_request;
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VX_generic_priority_encoder #(.N(NUMBER_REQUESTS)) VX_sel_bank(
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.valids(qual_valids),
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.index (qual_request_index),
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.found (qual_has_request)
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);
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assign reqq_empty = !qual_has_request;
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assign reqq_req_st0 = qual_has_request;
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assign reqq_req_tid_st0 = qual_request_index;
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assign reqq_req_addr_st0 = qual_addr [qual_request_index];
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assign reqq_req_writedata_st0 = qual_writedata[qual_request_index];
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assign reqq_req_rd_st0 = qual_rd;
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assign reqq_req_wb_st0 = qual_wb;
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assign reqq_req_warp_num_st0 = qual_warp_num;
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assign reqq_req_mem_read_st0 = qual_mem_read;
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assign reqq_req_mem_write_st0 = qual_mem_write;
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assign updated_valids = qual_valids & (~(1 << qual_request_index));
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always @(posedge clk) begin
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if (reset) begin
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use_per_valids <= 0;
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use_per_addr <= 0;
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use_per_writedata <= 0;
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use_per_rd <= 0;
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use_per_wb <= 0;
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use_per_warp_num <= 0;
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use_per_mem_read <= 0;
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use_per_mem_write <= 0;
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end else begin
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if (reqq_pop && qual_has_request) begin
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use_per_valids <= updated_valids;
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use_per_addr <= qual_addr;
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use_per_writedata <= qual_writedata;
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use_per_rd <= qual_rd;
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use_per_wb <= qual_wb;
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use_per_warp_num <= qual_warp_num;
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use_per_mem_read <= qual_mem_read;
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use_per_mem_write <= qual_mem_write;
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end
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// else if (reqq_pop) begin
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// use_per_valids[qual_request_index] <= updated_valids;
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// end
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end
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end
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endmodule |