83 lines
3.0 KiB
Verilog
83 lines
3.0 KiB
Verilog
`include "VX_define.vh"
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module VX_csr_pipe #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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input wire no_slot_csr,
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VX_csr_req_if csr_req_if,
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VX_wb_if writeback_if,
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VX_wb_if csr_wb_if,
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output wire stall_gpr_csr
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);
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wire[`NUM_THREADS-1:0] valid_s2;
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wire[`NW_BITS-1:0] warp_num_s2;
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wire[4:0] rd_s2;
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wire[1:0] wb_s2;
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wire is_csr_s2;
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wire[`CSR_ADDR_SIZE-1:0] csr_address_s2;
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wire[31:0] csr_read_data_s2;
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wire[31:0] csr_updated_data_s2;
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wire[31:0] csr_read_data_unqual;
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wire[31:0] csr_read_data;
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VX_csr_data #(
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.CORE_ID(CORE_ID)
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) csr_data (
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.clk (clk),
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.reset (reset),
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.read_addr (csr_req_if.csr_address),
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.read_data (csr_read_data_unqual),
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.write_enable (is_csr_s2),
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.write_data (csr_updated_data_s2[`CSR_WIDTH-1:0]),
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.write_addr (csr_address_s2),
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.warp_num (csr_req_if.warp_num),
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.wb_valid (| writeback_if.valid)
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);
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// wire hazard = (csr_address_s2 == csr_req_if.csr_address) & (warp_num_s2 == csr_req_if.warp_num) & |(valid_s2) & is_csr_s2;
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wire car_hazard = (csr_address_s2 == csr_req_if.csr_address) & (warp_num_s2 == csr_req_if.warp_num) & |(valid_s2) & is_csr_s2;
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assign csr_read_data = car_hazard ? csr_updated_data_s2 : csr_read_data_unqual;
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reg [31:0] csr_updated_data;
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always @(*) begin
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case (csr_req_if.alu_op)
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`ALU_CSR_RW: csr_updated_data = csr_req_if.csr_mask;
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`ALU_CSR_RS: csr_updated_data = csr_read_data | csr_req_if.csr_mask;
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`ALU_CSR_RC: csr_updated_data = csr_read_data & (32'hFFFFFFFF - csr_req_if.csr_mask);
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default: csr_updated_data = 32'hdeadbeef;
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endcase
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end
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VX_generic_register #(
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.N(32 + 32 + 12 + 1 + 1 + 2 + 5 + (`NW_BITS-1+1) + `NUM_THREADS)
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) csr_reg_s2 (
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.clk (clk),
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.reset(reset),
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.stall(no_slot_csr),
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.flush(1'b0),
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.in ({csr_req_if.valid, csr_req_if.warp_num, csr_req_if.rd, csr_req_if.wb, csr_req_if.is_csr, csr_req_if.csr_address, csr_req_if.is_io, csr_read_data , csr_updated_data }),
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.out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_address_s2 , csr_wb_if.is_io , csr_read_data_s2, csr_updated_data_s2})
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);
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assign csr_wb_if.valid = valid_s2;
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assign csr_wb_if.warp_num = warp_num_s2;
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assign csr_wb_if.rd = rd_s2;
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assign csr_wb_if.wb = wb_s2;
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genvar i;
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for (i = 0; i < `NUM_THREADS; i++) begin
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assign csr_wb_if.data[i] = (csr_address_s2 == `CSR_LTID) ? i :
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(csr_address_s2 == `CSR_GTID) ? (csr_read_data_s2 * `NUM_THREADS + i) :
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csr_read_data_s2;
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end
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assign stall_gpr_csr = no_slot_csr && csr_req_if.is_csr && (| csr_req_if.valid);
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endmodule
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