c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
99 lines
2.2 KiB
C++
99 lines
2.2 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <simobject.h>
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#include "pipeline.h"
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#include "cache_sim.h"
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namespace vortex {
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class Core;
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class ExeUnit : public SimObject<ExeUnit> {
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public:
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std::vector<SimPort<pipeline_trace_t*>> Inputs;
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std::vector<SimPort<pipeline_trace_t*>> Outputs;
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ExeUnit(const SimContext& ctx, Core* core, const char* name)
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: SimObject<ExeUnit>(ctx, name)
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, Inputs(ISSUE_WIDTH, this)
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, Outputs(ISSUE_WIDTH, this)
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, core_(core)
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{}
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virtual ~ExeUnit() {}
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virtual void reset() {}
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virtual void tick() = 0;
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protected:
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Core* core_;
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};
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///////////////////////////////////////////////////////////////////////////////
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class AluUnit : public ExeUnit {
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public:
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AluUnit(const SimContext& ctx, Core*);
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void tick();
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};
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///////////////////////////////////////////////////////////////////////////////
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class FpuUnit : public ExeUnit {
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public:
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FpuUnit(const SimContext& ctx, Core*);
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void tick();
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};
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///////////////////////////////////////////////////////////////////////////////
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class LsuUnit : public ExeUnit {
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public:
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LsuUnit(const SimContext& ctx, Core*);
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void reset();
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void tick();
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private:
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struct pending_req_t {
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pipeline_trace_t* trace;
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uint32_t count;
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};
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HashTable<pending_req_t> pending_rd_reqs_;
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uint32_t num_lanes_;
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pipeline_trace_t* fence_state_;
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uint64_t pending_loads_;
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bool fence_lock_;
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uint32_t input_idx_;
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};
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///////////////////////////////////////////////////////////////////////////////
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class SfuUnit : public ExeUnit {
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public:
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SfuUnit(const SimContext& ctx, Core*);
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void tick();
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private:
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uint32_t input_idx_;
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};
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} |