28 lines
660 B
Plaintext
28 lines
660 B
Plaintext
# load design
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read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/pipe_regs -I../../rtl/cache ../../rtl/Vortex.v
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# high-level synthesis
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proc; opt; fsm;; memory -nomap; opt
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# substitute block rams
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techmap -map map_rams.v
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# map remaining memories
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memory_map
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# low-level synthesis
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techmap; opt; flatten;; abc -lut6
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techmap -map map_xl_cells.v
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# add clock buffers
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select -set xl_clocks t:FDRE %x:+FDRE[C] t:FDRE %d
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iopadmap -inpad BUFGP O:I @xl_clocks
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# add io buffers
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select -set xl_nonclocks w:* t:BUFGP %x:+BUFGP[I] %d
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iopadmap -outpad OBUF I:O -inpad IBUF O:I @xl_nonclocks
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# write synthesis results
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write_edif synth.edif
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