37 lines
1.0 KiB
Verilog
37 lines
1.0 KiB
Verilog
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`include "VX_define.vh"
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module VX_csr_wrapper (
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VX_csr_req_if csr_req_if,
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VX_wb_if csr_wb_if
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);
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wire[`NUM_THREADS-1:0][31:0] thread_ids;
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wire[`NUM_THREADS-1:0][31:0] warp_ids;
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genvar cur_t, cur_tw;
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generate
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for (cur_t = 0; cur_t < `NUM_THREADS; cur_t = cur_t + 1) begin : thread_ids_init
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assign thread_ids[cur_t] = cur_t;
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end
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for (cur_tw = 0; cur_tw < `NUM_THREADS; cur_tw = cur_tw + 1) begin : warp_ids_init
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assign warp_ids[cur_tw] = {{(31-`NW_BITS-1){1'b0}}, csr_req_if.warp_num};
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end
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endgenerate
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assign csr_wb_if.valid = csr_req_if.valid;
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assign csr_wb_if.warp_num = csr_req_if.warp_num;
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assign csr_wb_if.rd = csr_req_if.rd;
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assign csr_wb_if.wb = csr_req_if.wb;
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wire thread_select = csr_req_if.csr_address == 12'h20;
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wire warp_select = csr_req_if.csr_address == 12'h21;
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assign csr_wb_if.csr_result = thread_select ? thread_ids :
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warp_select ? warp_ids :
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0;
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endmodule |