170 lines
6.7 KiB
Verilog
170 lines
6.7 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_cache_req_queue #(
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// Size of cache in bytes
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parameter CACHE_SIZE = 1024,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE = 16,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 8,
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// Size of a word in bytes
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parameter WORD_SIZE = 4,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUM_REQUESTS = 2,
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// Number of cycles to complete stage 1 (read from memory)
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parameter STAGE_1_CYCLES = 2,
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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parameter REQQ_SIZE = 8,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 8,
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// Dram Fill Rsp Queue Size
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parameter DFPQ_SIZE = 2,
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// Snoop Req Queue
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parameter SNRQ_SIZE = 8,
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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parameter CWBQ_SIZE = 8,
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// Dram Writeback Queue Size
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parameter DWBQ_SIZE = 4,
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// Dram Fill Req Queue Size
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parameter DFQQ_SIZE = 8,
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// Lower Level Cache Hit Queue Size
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parameter LLVQ_SIZE = 16,
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// Fill Invalidator Size {Fill invalidator must be active}
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parameter FILL_INVALIDAOR_SIZE = 16,
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// caceh requests tag size
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parameter CORE_TAG_WIDTH = 1
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) (
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input wire clk,
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input wire reset,
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// Enqueue Data
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input wire reqq_push,
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input wire [NUM_REQUESTS-1:0] bank_valids,
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input wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] bank_mem_read,
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input wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] bank_mem_write,
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input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] bank_writedata,
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input wire [NUM_REQUESTS-1:0][31:0] bank_addr,
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input wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] bank_tag,
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// Dequeue Data
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input wire reqq_pop,
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output wire reqq_req_st0,
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output wire [`LOG2UP(NUM_REQUESTS)-1:0] reqq_req_tid_st0,
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output wire [`WORD_SEL_BITS-1:0] reqq_req_mem_read_st0,
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output wire [`WORD_SEL_BITS-1:0] reqq_req_mem_write_st0,
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output wire [`WORD_WIDTH-1:0] reqq_req_writedata_st0,
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output wire [31:0] reqq_req_addr_st0,
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output wire [CORE_TAG_WIDTH-1:0] reqq_req_tag_st0,
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// State Data
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output wire reqq_empty,
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output wire reqq_full
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);
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wire [NUM_REQUESTS-1:0] out_per_valids;
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wire [NUM_REQUESTS-1:0][31:0] out_per_addr;
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wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] out_per_writedata;
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wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] out_per_mem_read;
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wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] out_per_mem_write;
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wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] out_per_tag;
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reg [NUM_REQUESTS-1:0] use_per_valids;
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reg [NUM_REQUESTS-1:0][31:0] use_per_addr;
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reg [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] use_per_writedata;
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reg [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] use_per_mem_read;
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reg [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] use_per_mem_write;
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reg [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] use_per_tag;
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wire [NUM_REQUESTS-1:0] qual_valids;
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wire [NUM_REQUESTS-1:0][31:0] qual_addr;
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wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] qual_writedata;
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wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] qual_mem_read;
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wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] qual_mem_write;
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wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] qual_tag;
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`DEBUG_BEGIN
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reg [NUM_REQUESTS-1:0] updated_valids;
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`DEBUG_END
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wire o_empty;
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wire use_empty = !(|use_per_valids);
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wire out_empty = !(|out_per_valids) || o_empty;
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wire push_qual = reqq_push && !reqq_full;
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wire pop_qual = !out_empty && use_empty;
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VX_generic_queue #(
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.DATAW($bits(bank_valids) + $bits(bank_addr) + $bits(bank_writedata) + $bits(bank_tag) + $bits(bank_mem_read) + $bits(bank_mem_write)),
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.SIZE(REQQ_SIZE)
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) reqq_queue (
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.clk (clk),
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.reset (reset),
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.push (push_qual),
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.data_in ({bank_valids, bank_addr, bank_writedata, bank_tag, bank_mem_read, bank_mem_write}),
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.pop (pop_qual),
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.data_out ({out_per_valids, out_per_addr, out_per_writedata, out_per_tag, out_per_mem_read, out_per_mem_write}),
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.empty (o_empty),
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.full (reqq_full)
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);
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wire[NUM_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUM_REQUESTS{~out_empty}};
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assign qual_valids = use_per_valids;
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assign qual_addr = use_per_addr;
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assign qual_writedata = use_per_writedata;
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assign qual_tag = use_per_tag;
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assign qual_mem_read = use_per_mem_read;
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assign qual_mem_write = use_per_mem_write;
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wire[`LOG2UP(NUM_REQUESTS)-1:0]qual_request_index;
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wire qual_has_request;
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VX_generic_priority_encoder #(
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.N(NUM_REQUESTS)
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) sel_bank (
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.valids(qual_valids),
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.index (qual_request_index),
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.found (qual_has_request)
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);
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assign reqq_empty = !qual_has_request;
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assign reqq_req_st0 = qual_has_request;
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assign reqq_req_tid_st0 = qual_request_index;
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assign reqq_req_addr_st0 = qual_addr[qual_request_index];
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assign reqq_req_writedata_st0 = qual_writedata[qual_request_index];
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assign reqq_req_tag_st0 = qual_tag[qual_request_index];
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assign reqq_req_mem_read_st0 = qual_mem_read [qual_request_index];
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assign reqq_req_mem_write_st0 = qual_mem_write[qual_request_index];
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always @(*) begin
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updated_valids = qual_valids;
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if (qual_has_request) begin
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updated_valids[qual_request_index] = 0;
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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use_per_valids <= 0;
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end else begin
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if (pop_qual) begin
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use_per_valids <= real_out_per_valids;
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use_per_addr <= out_per_addr;
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use_per_writedata <= out_per_writedata;
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use_per_tag <= out_per_tag;
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use_per_mem_read <= out_per_mem_read;
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use_per_mem_write <= out_per_mem_write;
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end else if (reqq_pop) begin
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use_per_valids[qual_request_index] <= 0;
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end
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end
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end
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endmodule |