160 lines
4.8 KiB
Verilog
160 lines
4.8 KiB
Verilog
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`include "VX_define.v"
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module VX_execute (
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input wire[4:0] in_rd,
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input wire[4:0] in_rs1,
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input wire[4:0] in_rs2,
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input wire[31:0] in_a_reg_data[`NT_M1:0],
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input wire[31:0] in_b_reg_data[`NT_M1:0],
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input wire[4:0] in_alu_op,
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input wire[1:0] in_wb,
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input wire in_rs2_src, // NEW
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input wire[31:0] in_itype_immed, // new
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input wire[2:0] in_mem_read, // NEW
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input wire[2:0] in_mem_write, // NEW
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input wire[31:0] in_PC_next,
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input wire[2:0] in_branch_type,
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input wire[19:0] in_upper_immed,
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input wire[11:0] in_csr_address, // done
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input wire in_is_csr, // done
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input wire[31:0] in_csr_data, // done
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input wire[31:0] in_csr_mask, // done
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input wire in_jal,
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input wire[31:0] in_jal_offset,
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input wire[31:0] in_curr_PC,
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input wire in_valid[`NT_M1:0],
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output wire[11:0] out_csr_address,
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output wire out_is_csr,
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output reg[31:0] out_csr_result,
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output reg[31:0] out_alu_result[`NT_M1:0],
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output wire[4:0] out_rd,
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output wire[1:0] out_wb,
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output wire[4:0] out_rs1,
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output wire[4:0] out_rs2,
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output wire[31:0] out_a_reg_data[`NT_M1:0],
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output wire[31:0] out_b_reg_data[`NT_M1:0],
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output wire[2:0] out_mem_read,
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output wire[2:0] out_mem_write,
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output wire out_jal,
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output wire[31:0] out_jal_dest,
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output wire[31:0] out_branch_offset,
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output wire out_branch_stall,
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output wire[31:0] out_PC_next,
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output wire out_valid[`NT_M1:0]
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);
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// VX_alu vx_alu(
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// .in_reg_data (in_reg_data),
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// .in_rs2_src (in_rs2_src),
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// .in_itype_immed(in_itype_immed),
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// .in_upper_immed(in_upper_immed),
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// .in_alu_op (in_alu_op),
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// .in_csr_data (in_csr_data),
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// .in_curr_PC (in_curr_PC),
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// .out_alu_result(out_alu_result)
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// );
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// genvar index;
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// reg[5:0] index_2;
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// generate
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// for (index=0; index < `NT; index=index+1)
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// begin: gen_code_label
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// assign index_2 = index * 2;
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// VX_alu vx_alu(
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// .in_reg_data (in_reg_data[(index_2+1):(index_2)]),
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// .in_rs2_src (in_rs2_src),
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// .in_itype_immed(in_itype_immed),
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// .in_upper_immed(in_upper_immed),
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// .in_alu_op (in_alu_op),
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// .in_csr_data (in_csr_data),
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// .in_curr_PC (in_curr_PC),
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// .out_alu_result(out_alu_result[index])
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// );
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// end
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// endgenerate
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// genvar index_out_reg;
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// generate
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// for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
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// begin
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// VX_alu vx_alu_0(
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// // .in_reg_data (in_reg_data[1:0]),
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// .in_1 (in_a_reg_data[index_out_reg]),
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// .in_2 (in_b_reg_data[index_out_reg]),
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// .in_rs2_src (in_rs2_src),
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// .in_itype_immed(in_itype_immed),
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// .in_upper_immed(in_upper_immed),
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// .in_alu_op (in_alu_op),
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// .in_csr_data (in_csr_data),
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// .in_curr_PC (in_curr_PC),
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// .out_alu_result(out_alu_result[index_out_reg])
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// );
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// end
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// endgenerate
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VX_alu vx_alu_0(
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.in_1 (in_a_reg_data[0]),
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.in_2 (in_b_reg_data[0]),
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.in_rs2_src (in_rs2_src),
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.in_itype_immed(in_itype_immed),
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.in_upper_immed(in_upper_immed),
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.in_alu_op (in_alu_op),
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.in_csr_data (in_csr_data),
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.in_curr_PC (in_curr_PC),
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.out_alu_result(out_alu_result[0])
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);
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VX_alu vx_alu_1(
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.in_1 (in_a_reg_data[1]),
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.in_2 (in_b_reg_data[1]),
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.in_rs2_src (in_rs2_src),
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.in_itype_immed(in_itype_immed),
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.in_upper_immed(in_upper_immed),
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.in_alu_op (in_alu_op),
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.in_csr_data (in_csr_data),
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.in_curr_PC (in_curr_PC),
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.out_alu_result(out_alu_result[1])
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);
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assign out_jal_dest = $signed(in_a_reg_data[0]) + $signed(in_jal_offset);
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assign out_jal = in_jal;
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always @(*) begin
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case(in_alu_op)
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`CSR_ALU_RW: out_csr_result = in_csr_mask;
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`CSR_ALU_RS: out_csr_result = in_csr_data | in_csr_mask;
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`CSR_ALU_RC: out_csr_result = in_csr_data & (32'hFFFFFFFF - in_csr_mask);
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default: out_csr_result = 32'hdeadbeef;
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endcase
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end
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assign out_branch_stall = ((in_branch_type != `NO_BRANCH) || in_jal ) ? `STALL : `NO_STALL;
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assign out_rd = in_rd;
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assign out_wb = in_wb;
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assign out_mem_read = in_mem_read;
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assign out_mem_write = in_mem_write;
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assign out_rs1 = in_rs1;
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assign out_a_reg_data = in_a_reg_data;
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assign out_b_reg_data = in_b_reg_data;
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assign out_rs2 = in_rs2;
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assign out_PC_next = in_PC_next;
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assign out_is_csr = in_is_csr;
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assign out_csr_address = in_csr_address;
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assign out_branch_offset = in_itype_immed;
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assign out_valid = in_valid;
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endmodule // VX_execute
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