83 lines
2.6 KiB
Verilog
83 lines
2.6 KiB
Verilog
`include "VX_define.vh"
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module VX_csr_arb #(
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parameter NUM_REQS = 1,
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parameter DATA_WIDTH = 1,
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parameter BUFFERED_REQ = 0,
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parameter BUFFERED_RSP = 0,
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parameter DATA_SIZE = (DATA_WIDTH / 8),
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parameter ADDR_WIDTH = 32 - `CLOG2(DATA_SIZE),
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parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
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) (
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input wire clk,
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input wire reset,
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input wire [LOG_NUM_REQS-1:0] request_id,
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// input requests
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input wire req_valid_in,
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input wire [ADDR_WIDTH-1:0] req_addr_in,
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input wire req_rw_in,
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input wire [DATA_WIDTH-1:0] req_data_in,
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output wire req_ready_in,
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// output request
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output wire [NUM_REQS-1:0] req_valid_out,
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output wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] req_addr_out,
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output wire [NUM_REQS-1:0] req_rw_out,
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output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] req_data_out,
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input wire [NUM_REQS-1:0] req_ready_out,
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// input response
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input wire [NUM_REQS-1:0] rsp_valid_in,
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input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data_in,
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output wire [NUM_REQS-1:0] rsp_ready_in,
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// output response
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output wire rsp_valid_out,
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output wire [DATA_WIDTH-1:0] rsp_data_out,
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input wire rsp_ready_out
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);
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localparam REQ_DATAW = ADDR_WIDTH + 1 + DATA_WIDTH;
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localparam RSP_DATAW = DATA_WIDTH;
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wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_merged_data_out;
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign {req_addr_out[i], req_rw_out[i], req_data_out[i]} = req_merged_data_out[i];
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end
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VX_stream_demux #(
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.NUM_REQS (NUM_REQS),
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.DATAW (REQ_DATAW),
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.BUFFERED (BUFFERED_REQ)
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) req_demux (
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.clk (clk),
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.reset (reset),
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.sel (request_id),
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.valid_in (req_valid_in),
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.data_in ({req_addr_in, req_rw_in, req_data_in}),
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.ready_in (req_ready_in),
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.valid_out (req_valid_out),
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.data_out (req_merged_data_out),
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.ready_out (req_ready_out)
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);
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VX_stream_arbiter #(
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.NUM_REQS (NUM_REQS),
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.DATAW (RSP_DATAW),
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.BUFFERED (BUFFERED_RSP),
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.TYPE ("X") // fixed arbitration
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) rsp_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (rsp_valid_in),
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.data_in (rsp_data_in),
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.ready_in (rsp_ready_in),
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.valid_out (rsp_valid_out),
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.data_out (rsp_data_out),
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.ready_out (rsp_ready_out)
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);
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endmodule
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