428 lines
17 KiB
Verilog
428 lines
17 KiB
Verilog
`include "VX_define.vh"
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module VX_mem_unit # (
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_VX_mem_unit
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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VX_perf_memsys_if perf_memsys_if,
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`endif
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// Core <-> Dcache
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VX_dcache_req_if dcache_req_if,
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VX_dcache_rsp_if dcache_rsp_if,
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// Core <-> Icache
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VX_icache_req_if icache_req_if,
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VX_icache_rsp_if icache_rsp_if,
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// Memory
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VX_mem_req_if mem_req_if,
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VX_mem_rsp_if mem_rsp_if
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);
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`ifdef PERF_ENABLE
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VX_perf_cache_if perf_icache_if(), perf_dcache_if(), perf_smem_if();
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`endif
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VX_mem_req_if #(
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.DATA_WIDTH (`IMEM_DATA_WIDTH),
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.ADDR_WIDTH (`IMEM_ADDR_WIDTH),
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.TAG_WIDTH (`IMEM_TAG_WIDTH)
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) icache_mem_req_if();
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VX_mem_rsp_if #(
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.DATA_WIDTH (`IMEM_DATA_WIDTH),
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.TAG_WIDTH (`IMEM_TAG_WIDTH)
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) icache_mem_rsp_if();
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VX_mem_req_if #(
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.DATA_WIDTH (`DMEM_DATA_WIDTH),
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.ADDR_WIDTH (`DMEM_ADDR_WIDTH),
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.TAG_WIDTH (`DMEM_TAG_WIDTH)
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) dcache_mem_req_if();
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VX_mem_rsp_if #(
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.DATA_WIDTH (`DMEM_DATA_WIDTH),
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.TAG_WIDTH (`DMEM_TAG_WIDTH)
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) dcache_mem_rsp_if();
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VX_dcache_req_if #(
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.NUM_REQS (`DNUM_REQS),
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.WORD_SIZE (`DWORD_SIZE),
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.TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
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) dcache_req_tmp_if();
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VX_dcache_rsp_if #(
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.NUM_REQS (`DNUM_REQS),
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.WORD_SIZE (`DWORD_SIZE),
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.TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
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) dcache_rsp_tmp_if();
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`RESET_RELAY (icache_reset);
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`RESET_RELAY (dcache_reset);
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`RESET_RELAY (mem_arb_reset);
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VX_cache #(
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.CACHE_ID (`ICACHE_ID),
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.CACHE_SIZE (`ICACHE_SIZE),
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.CACHE_LINE_SIZE (`ICACHE_LINE_SIZE),
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.NUM_BANKS (`INUM_BANKS),
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.WORD_SIZE (`IWORD_SIZE),
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.NUM_REQS (1),
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.CREQ_SIZE (`ICREQ_SIZE),
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.CRSQ_SIZE (`ICRSQ_SIZE),
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.MSHR_SIZE (`IMSHR_SIZE),
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.MRSQ_SIZE (`IMRSQ_SIZE),
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.MREQ_SIZE (`IMREQ_SIZE),
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.WRITE_ENABLE (0),
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.CORE_TAG_WIDTH (`ICORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (`ICORE_TAG_ID_BITS),
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.MEM_TAG_WIDTH (`IMEM_TAG_WIDTH)
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) icache (
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`SCOPE_BIND_VX_mem_unit_icache
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.clk (clk),
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.reset (icache_reset),
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// Core request
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.core_req_valid (icache_req_if.valid),
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.core_req_rw (1'b0),
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.core_req_byteen ({`IWORD_SIZE{1'b1}}),
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.core_req_addr (icache_req_if.addr),
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.core_req_data ('x),
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.core_req_tag (icache_req_if.tag),
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.core_req_ready (icache_req_if.ready),
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// Core response
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.core_rsp_valid (icache_rsp_if.valid),
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.core_rsp_data (icache_rsp_if.data),
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.core_rsp_tag (icache_rsp_if.tag),
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.core_rsp_ready (icache_rsp_if.ready),
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`UNUSED_PIN (core_rsp_tmask),
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`ifdef PERF_ENABLE
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.perf_cache_if (perf_icache_if),
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`endif
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// Memory Request
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.mem_req_valid (icache_mem_req_if.valid),
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.mem_req_rw (icache_mem_req_if.rw),
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.mem_req_byteen (icache_mem_req_if.byteen),
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.mem_req_addr (icache_mem_req_if.addr),
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.mem_req_data (icache_mem_req_if.data),
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.mem_req_tag (icache_mem_req_if.tag),
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.mem_req_ready (icache_mem_req_if.ready),
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// Memory response
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.mem_rsp_valid (icache_mem_rsp_if.valid),
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.mem_rsp_data (icache_mem_rsp_if.data),
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.mem_rsp_tag (icache_mem_rsp_if.tag),
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.mem_rsp_ready (icache_mem_rsp_if.ready)
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);
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VX_cache #(
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.CACHE_ID (`DCACHE_ID),
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.CACHE_SIZE (`DCACHE_SIZE),
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.CACHE_LINE_SIZE (`DCACHE_LINE_SIZE),
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.NUM_BANKS (`DNUM_BANKS),
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.NUM_PORTS (`DNUM_PORTS),
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.WORD_SIZE (`DWORD_SIZE),
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.NUM_REQS (`DNUM_REQS),
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.CREQ_SIZE (`DCREQ_SIZE),
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.CRSQ_SIZE (`DCRSQ_SIZE),
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.MSHR_SIZE (`DMSHR_SIZE),
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.MRSQ_SIZE (`DMRSQ_SIZE),
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.MREQ_SIZE (`DMREQ_SIZE),
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.WRITE_ENABLE (1),
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.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE),
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.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS-`SM_ENABLE),
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.MEM_TAG_WIDTH (`DMEM_TAG_WIDTH),
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.NC_ENABLE (1)
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) dcache (
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`SCOPE_BIND_VX_mem_unit_dcache
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.clk (clk),
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.reset (dcache_reset),
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// Core req
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.core_req_valid (dcache_req_tmp_if.valid),
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.core_req_rw (dcache_req_tmp_if.rw),
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.core_req_byteen (dcache_req_tmp_if.byteen),
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.core_req_addr (dcache_req_tmp_if.addr),
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.core_req_data (dcache_req_tmp_if.data),
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.core_req_tag (dcache_req_tmp_if.tag),
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.core_req_ready (dcache_req_tmp_if.ready),
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// Core response
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.core_rsp_valid (dcache_rsp_tmp_if.valid),
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.core_rsp_tmask (dcache_rsp_tmp_if.tmask),
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.core_rsp_data (dcache_rsp_tmp_if.data),
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.core_rsp_tag (dcache_rsp_tmp_if.tag),
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.core_rsp_ready (dcache_rsp_tmp_if.ready),
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`ifdef PERF_ENABLE
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.perf_cache_if (perf_dcache_if),
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`endif
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// Memory request
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.mem_req_valid (dcache_mem_req_if.valid),
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.mem_req_rw (dcache_mem_req_if.rw),
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.mem_req_byteen (dcache_mem_req_if.byteen),
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.mem_req_addr (dcache_mem_req_if.addr),
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.mem_req_data (dcache_mem_req_if.data),
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.mem_req_tag (dcache_mem_req_if.tag),
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.mem_req_ready (dcache_mem_req_if.ready),
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// Memory response
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.mem_rsp_valid (dcache_mem_rsp_if.valid),
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.mem_rsp_data (dcache_mem_rsp_if.data),
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.mem_rsp_tag (dcache_mem_rsp_if.tag),
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.mem_rsp_ready (dcache_mem_rsp_if.ready)
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);
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if (`SM_ENABLE) begin
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VX_dcache_req_if #(
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.NUM_REQS (`DNUM_REQS),
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.WORD_SIZE (`DWORD_SIZE),
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.TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
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) smem_req_if();
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VX_dcache_rsp_if #(
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.NUM_REQS (`DNUM_REQS),
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.WORD_SIZE (`DWORD_SIZE),
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.TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
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) smem_rsp_if();
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`RESET_RELAY (smem_arb_reset);
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`RESET_RELAY (smem_reset);
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VX_smem_arb #(
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.NUM_REQS (2),
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.LANES (`NUM_THREADS),
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.DATA_SIZE (4),
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.TAG_IN_WIDTH (`DCORE_TAG_WIDTH),
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.TYPE ("P"),
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.BUFFERED_REQ (2),
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.BUFFERED_RSP (1)
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) smem_arb (
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.clk (clk),
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.reset (smem_arb_reset),
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// input request
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.req_valid_in (dcache_req_if.valid),
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.req_rw_in (dcache_req_if.rw),
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.req_byteen_in (dcache_req_if.byteen),
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.req_addr_in (dcache_req_if.addr),
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.req_data_in (dcache_req_if.data),
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.req_tag_in (dcache_req_if.tag),
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.req_ready_in (dcache_req_if.ready),
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// output requests
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.req_valid_out ({smem_req_if.valid, dcache_req_tmp_if.valid}),
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.req_rw_out ({smem_req_if.rw, dcache_req_tmp_if.rw}),
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.req_byteen_out ({smem_req_if.byteen, dcache_req_tmp_if.byteen}),
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.req_addr_out ({smem_req_if.addr, dcache_req_tmp_if.addr}),
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.req_data_out ({smem_req_if.data, dcache_req_tmp_if.data}),
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.req_tag_out ({smem_req_if.tag, dcache_req_tmp_if.tag}),
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.req_ready_out ({smem_req_if.ready, dcache_req_tmp_if.ready}),
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// input responses
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.rsp_valid_in ({smem_rsp_if.valid, dcache_rsp_tmp_if.valid}),
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.rsp_tmask_in ({smem_rsp_if.tmask, dcache_rsp_tmp_if.tmask}),
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.rsp_data_in ({smem_rsp_if.data, dcache_rsp_tmp_if.data}),
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.rsp_tag_in ({smem_rsp_if.tag, dcache_rsp_tmp_if.tag}),
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.rsp_ready_in ({smem_rsp_if.ready, dcache_rsp_tmp_if.ready}),
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// output response
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.rsp_valid_out (dcache_rsp_if.valid),
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.rsp_tmask_out (dcache_rsp_if.tmask),
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.rsp_tag_out (dcache_rsp_if.tag),
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.rsp_data_out (dcache_rsp_if.data),
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.rsp_ready_out (dcache_rsp_if.ready)
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);
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VX_shared_mem #(
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.CACHE_ID (`SCACHE_ID),
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.CACHE_SIZE (`SMEM_SIZE),
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.NUM_BANKS (`SNUM_BANKS),
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.WORD_SIZE (`SWORD_SIZE),
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.NUM_REQS (`SNUM_REQS),
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.CREQ_SIZE (`SCREQ_SIZE),
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.CRSQ_SIZE (`SCRSQ_SIZE),
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.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE),
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.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS-`SM_ENABLE),
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.BANK_ADDR_OFFSET (`SBANK_ADDR_OFFSET)
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) smem (
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.clk (clk),
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.reset (smem_reset),
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`ifdef PERF_ENABLE
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.perf_cache_if (perf_smem_if),
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`endif
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// Core request
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.core_req_valid (smem_req_if.valid),
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.core_req_rw (smem_req_if.rw),
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.core_req_byteen (smem_req_if.byteen),
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.core_req_addr (smem_req_if.addr),
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.core_req_data (smem_req_if.data),
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.core_req_tag (smem_req_if.tag),
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.core_req_ready (smem_req_if.ready),
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// Core response
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.core_rsp_valid (smem_rsp_if.valid),
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.core_rsp_tmask (smem_rsp_if.tmask),
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.core_rsp_data (smem_rsp_if.data),
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.core_rsp_tag (smem_rsp_if.tag),
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.core_rsp_ready (smem_rsp_if.ready)
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);
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end else begin
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// core to D-cache request
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for (genvar i = 0; i < `DNUM_REQS; ++i) begin
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VX_skid_buffer #(
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.DATAW ((32-`CLOG2(`DWORD_SIZE)) + 1 + `DWORD_SIZE + (8*`DWORD_SIZE) + `DCORE_TAG_WIDTH)
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) req_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (dcache_req_if.valid[i]),
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.data_in ({dcache_req_if.addr[i], dcache_req_if.rw[i], dcache_req_if.byteen[i], dcache_req_if.data[i], dcache_req_if.tag[i]}),
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.ready_in (dcache_req_if.ready[i]),
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.valid_out (dcache_req_tmp_if.valid[i]),
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.data_out ({dcache_req_tmp_if.addr[i], dcache_req_tmp_if.rw[i], dcache_req_tmp_if.byteen[i], dcache_req_tmp_if.data[i], dcache_req_tmp_if.tag[i]}),
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.ready_out (dcache_req_tmp_if.ready[i])
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);
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end
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// D-cache to core reponse
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assign dcache_rsp_if.valid = dcache_rsp_tmp_if.valid;
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assign dcache_rsp_if.tmask = dcache_rsp_tmp_if.tmask;
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assign dcache_rsp_if.tag = dcache_rsp_tmp_if.tag;
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assign dcache_rsp_if.data = dcache_rsp_tmp_if.data;
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assign dcache_rsp_tmp_if.ready = dcache_rsp_if.ready;
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end
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wire [`DMEM_TAG_WIDTH-1:0] icache_mem_req_tag = `DMEM_TAG_WIDTH'(icache_mem_req_if.tag);
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wire [`DMEM_TAG_WIDTH-1:0] icache_mem_rsp_tag;
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assign icache_mem_rsp_if.tag = icache_mem_rsp_tag[`IMEM_TAG_WIDTH-1:0];
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`UNUSED_VAR (icache_mem_rsp_tag)
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VX_mem_arb #(
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.NUM_REQS (2),
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.DATA_WIDTH (`DMEM_DATA_WIDTH),
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.ADDR_WIDTH (`DMEM_ADDR_WIDTH),
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.TAG_IN_WIDTH (`DMEM_TAG_WIDTH),
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.TYPE ("R"),
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.TAG_SEL_IDX (1), // Skip 0 for NC flag
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.BUFFERED_REQ (1),
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.BUFFERED_RSP (2)
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) mem_arb (
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.clk (clk),
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.reset (mem_arb_reset),
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// Source request
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.req_valid_in ({dcache_mem_req_if.valid, icache_mem_req_if.valid}),
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.req_rw_in ({dcache_mem_req_if.rw, icache_mem_req_if.rw}),
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.req_byteen_in ({dcache_mem_req_if.byteen, icache_mem_req_if.byteen}),
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.req_addr_in ({dcache_mem_req_if.addr, icache_mem_req_if.addr}),
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.req_data_in ({dcache_mem_req_if.data, icache_mem_req_if.data}),
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.req_tag_in ({dcache_mem_req_if.tag, icache_mem_req_tag}),
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.req_ready_in ({dcache_mem_req_if.ready, icache_mem_req_if.ready}),
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// Memory request
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.req_valid_out (mem_req_if.valid),
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.req_rw_out (mem_req_if.rw),
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.req_byteen_out (mem_req_if.byteen),
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.req_addr_out (mem_req_if.addr),
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.req_data_out (mem_req_if.data),
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.req_tag_out (mem_req_if.tag),
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.req_ready_out (mem_req_if.ready),
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// Source response
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.rsp_valid_out ({dcache_mem_rsp_if.valid, icache_mem_rsp_if.valid}),
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.rsp_data_out ({dcache_mem_rsp_if.data, icache_mem_rsp_if.data}),
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.rsp_tag_out ({dcache_mem_rsp_if.tag, icache_mem_rsp_tag}),
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.rsp_ready_out ({dcache_mem_rsp_if.ready, icache_mem_rsp_if.ready}),
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// Memory response
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.rsp_valid_in (mem_rsp_if.valid),
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.rsp_tag_in (mem_rsp_if.tag),
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.rsp_data_in (mem_rsp_if.data),
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.rsp_ready_in (mem_rsp_if.ready)
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);
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`ifdef PERF_ENABLE
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assign perf_memsys_if.icache_reads = perf_icache_if.reads;
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assign perf_memsys_if.icache_read_misses = perf_icache_if.read_misses;
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assign perf_memsys_if.icache_pipe_stalls = perf_icache_if.pipe_stalls;
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assign perf_memsys_if.icache_crsp_stalls = perf_icache_if.crsp_stalls;
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assign perf_memsys_if.dcache_reads = perf_dcache_if.reads;
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assign perf_memsys_if.dcache_writes = perf_dcache_if.writes;
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assign perf_memsys_if.dcache_read_misses = perf_dcache_if.read_misses;
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assign perf_memsys_if.dcache_write_misses= perf_dcache_if.write_misses;
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assign perf_memsys_if.dcache_bank_stalls = perf_dcache_if.bank_stalls;
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assign perf_memsys_if.dcache_mshr_stalls = perf_dcache_if.mshr_stalls;
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assign perf_memsys_if.dcache_pipe_stalls = perf_dcache_if.pipe_stalls;
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assign perf_memsys_if.dcache_crsp_stalls = perf_dcache_if.crsp_stalls;
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if (`SM_ENABLE) begin
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assign perf_memsys_if.smem_reads = perf_smem_if.reads;
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assign perf_memsys_if.smem_writes = perf_smem_if.writes;
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assign perf_memsys_if.smem_bank_stalls = perf_smem_if.bank_stalls;
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end else begin
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assign perf_memsys_if.smem_reads = 0;
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assign perf_memsys_if.smem_writes = 0;
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assign perf_memsys_if.smem_bank_stalls = 0;
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end
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reg [`PERF_CTR_BITS-1:0] perf_mem_lat_per_cycle;
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always @(posedge clk) begin
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if (reset) begin
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perf_mem_lat_per_cycle <= 0;
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end else begin
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perf_mem_lat_per_cycle <= perf_mem_lat_per_cycle +
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`PERF_CTR_BITS'($signed(2'((mem_req_if.valid && !mem_req_if.rw && mem_req_if.ready) && !(mem_rsp_if.valid && mem_rsp_if.ready)) -
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2'((mem_rsp_if.valid && mem_rsp_if.ready) && !(mem_req_if.valid && !mem_req_if.rw && mem_req_if.ready))));
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end
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end
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reg [`PERF_CTR_BITS-1:0] perf_mem_reads;
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reg [`PERF_CTR_BITS-1:0] perf_mem_writes;
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reg [`PERF_CTR_BITS-1:0] perf_mem_lat;
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reg [`PERF_CTR_BITS-1:0] perf_mem_stalls;
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always @(posedge clk) begin
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if (reset) begin
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perf_mem_reads <= 0;
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perf_mem_writes <= 0;
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perf_mem_lat <= 0;
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perf_mem_stalls <= 0;
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end else begin
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if (mem_req_if.valid && mem_req_if.ready && !mem_req_if.rw) begin
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perf_mem_reads <= perf_mem_reads + `PERF_CTR_BITS'd1;
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end
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if (mem_req_if.valid && mem_req_if.ready && mem_req_if.rw) begin
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perf_mem_writes <= perf_mem_writes + `PERF_CTR_BITS'd1;
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end
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if (mem_req_if.valid && !mem_req_if.ready) begin
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perf_mem_stalls <= perf_mem_stalls + `PERF_CTR_BITS'd1;
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end
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perf_mem_lat <= perf_mem_lat + perf_mem_lat_per_cycle;
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end
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end
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assign perf_memsys_if.mem_reads = perf_mem_reads;
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assign perf_memsys_if.mem_writes = perf_mem_writes;
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assign perf_memsys_if.mem_latency = perf_mem_lat;
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assign perf_memsys_if.mem_stalls = perf_mem_stalls;
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`endif
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endmodule
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