c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
45 lines
1.1 KiB
C++
45 lines
1.1 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <util.h>
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#include <VX_types.h>
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#include <array>
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namespace vortex {
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class BaseDCRS {
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public:
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uint32_t read(uint32_t addr) const {
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uint32_t state = VX_DCR_BASE_STATE(addr);
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return states_.at(state);
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}
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void write(uint32_t addr, uint32_t value) {
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uint32_t state = VX_DCR_BASE_STATE(addr);
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states_.at(state) = value;
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}
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private:
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std::array<uint32_t, VX_DCR_BASE_STATE_COUNT> states_;
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};
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class DCRS {
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public:
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void write(uint32_t addr, uint32_t value);
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BaseDCRS base_dcrs;
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};
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} |