422 lines
8.9 KiB
Systemverilog
422 lines
8.9 KiB
Systemverilog
`ifndef VX_CONFIG
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`define VX_CONFIG
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`include "VX_user_config.vh"
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`ifndef NUM_CLUSTERS
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`define NUM_CLUSTERS 1
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`endif
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`ifndef NUM_CORES
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`define NUM_CORES 4
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`endif
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`ifndef NUM_WARPS
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`define NUM_WARPS 4
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`endif
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`ifndef NUM_THREADS
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`define NUM_THREADS 4
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`endif
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`ifndef NUM_BARRIERS
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`define NUM_BARRIERS 4
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`endif
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`ifndef L2_ENABLE
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`define L2_ENABLE 0
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`endif
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`ifndef L3_ENABLE
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`define L3_ENABLE 0
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`endif
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`ifndef SM_ENABLE
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`define SM_ENABLE 1
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`endif
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`ifndef GLOBAL_BLOCK_SIZE
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`define GLOBAL_BLOCK_SIZE 64
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`endif
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`ifndef L1_BLOCK_SIZE
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`define L1_BLOCK_SIZE (`NUM_THREADS * 4)
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`endif
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`ifndef STARTUP_ADDR
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`define STARTUP_ADDR 32'h80000000
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`endif
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`ifndef SHARED_MEM_BASE_ADDR
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`define SHARED_MEM_BASE_ADDR 32'h6FFFF000
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`endif
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`ifndef IO_BUS_BASE_ADDR
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`define IO_BUS_BASE_ADDR 32'hFF000000
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`endif
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`ifndef IO_BUS_ADDR_COUT
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`define IO_BUS_ADDR_COUT 32'hFFFFFFFC
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`endif
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`ifndef FRAME_BUFFER_BASE_ADDR
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`define FRAME_BUFFER_BASE_ADDR 32'hFF000000
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`endif
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`ifndef FRAME_BUFFER_WIDTH
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`define FRAME_BUFFER_WIDTH 16'd1920
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`endif
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`ifndef FRAME_BUFFER_HEIGHT
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`define FRAME_BUFFER_HEIGHT 16'd1080
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`endif
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`define FRAME_BUFFER_SIZE (FRAME_BUFFER_WIDTH * FRAME_BUFFER_HEIGHT)
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`ifndef EXT_M_DISABLE
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`define EXT_M_ENABLE
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`endif
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`ifndef EXT_F_DISABLE
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`define EXT_F_ENABLE
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`endif
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// Device identification
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`define VENDOR_ID 0
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`define ARCHITECTURE_ID 0
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`define IMPLEMENTATION_ID 0
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///////////////////////////////////////////////////////////////////////////////
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`ifndef LATENCY_IMUL
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`define LATENCY_IMUL 3
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`endif
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`ifndef LATENCY_FNCOMP
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`define LATENCY_FNCOMP 2
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`endif
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`ifndef LATENCY_FMA
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`define LATENCY_FMA 4
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`endif
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`ifndef LATENCY_FDIV
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`ifdef ALTERA_S10
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`define LATENCY_FDIV 34
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`else
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`define LATENCY_FDIV 20
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`endif
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`endif
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`ifndef LATENCY_FSQRT
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`ifdef ALTERA_S10
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`define LATENCY_FSQRT 25
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`else
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`define LATENCY_FSQRT 15
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`endif
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`endif
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`ifndef LATENCY_ITOF
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`define LATENCY_ITOF 7
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`endif
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`ifndef LATENCY_FTOI
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`define LATENCY_FTOI 3
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`endif
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`ifndef LATENCY_FDIVSQRT
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`define LATENCY_FDIVSQRT 32
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`endif
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`ifndef LATENCY_FCONV
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`define LATENCY_FCONV 4
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`endif
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// CSR Addresses //////////////////////////////////////////////////////////////
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// User Floating-Point CSRs
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`define CSR_FFLAGS 12'h001
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`define CSR_FRM 12'h002
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`define CSR_FCSR 12'h003
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// SIMT CSRs
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`define CSR_LTID 12'h020
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`define CSR_LWID 12'h021
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`define CSR_GTID 12'h022
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`define CSR_GWID 12'h023
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`define CSR_GCID 12'h024
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`define CSR_NT 12'h025
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`define CSR_NW 12'h026
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`define CSR_NC 12'h027
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`define CSR_SATP 12'h180
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`define CSR_PMPCFG0 12'h3A0
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`define CSR_PMPADDR0 12'h3B0
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`define CSR_MSTATUS 12'h300
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`define CSR_MISA 12'h301
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`define CSR_MEDELEG 12'h302
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`define CSR_MIDELEG 12'h303
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`define CSR_MIE 12'h304
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`define CSR_MTVEC 12'h305
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`define CSR_MEPC 12'h341
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// Machine Counter/Timers
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`define CSR_MCYCLE 12'hB00
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`define CSR_MCYCLE_H 12'hB80
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`define CSR_MINSTRET 12'hB02
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`define CSR_MINSTRET_H 12'hB82
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// Machine Performance-monitoring counters
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// PERF: pipeline
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`define CSR_MPM_IBUF_ST 12'hB03
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`define CSR_MPM_IBUF_ST_H 12'hB83
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`define CSR_MPM_SCRB_ST 12'hB04
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`define CSR_MPM_SCRB_ST_H 12'hB84
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`define CSR_MPM_ALU_ST 12'hB05
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`define CSR_MPM_ALU_ST_H 12'hB85
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`define CSR_MPM_LSU_ST 12'hB06
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`define CSR_MPM_LSU_ST_H 12'hB86
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`define CSR_MPM_CSR_ST 12'hB07
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`define CSR_MPM_CSR_ST_H 12'hB87
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`define CSR_MPM_MUL_ST 12'hB08
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`define CSR_MPM_MUL_ST_H 12'hB88
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`define CSR_MPM_FPU_ST 12'hB09
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`define CSR_MPM_FPU_ST_H 12'hB89
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`define CSR_MPM_GPU_ST 12'hB0A
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`define CSR_MPM_GPU_ST_H 12'hB8A
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// PERF: icache
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`define CSR_MPM_ICACHE_READS 12'hB0B // total reads
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`define CSR_MPM_ICACHE_READS_H 12'hB8B
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`define CSR_MPM_ICACHE_MISS_R 12'hB0C // total misses
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`define CSR_MPM_ICACHE_MISS_R_H 12'hB8C
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`define CSR_MPM_ICACHE_PIPE_ST 12'hB0D // pipeline stalls
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`define CSR_MPM_ICACHE_PIPE_ST_H 12'hB8D
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`define CSR_MPM_ICACHE_CRSP_ST 12'hB0E // core response stalls
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`define CSR_MPM_ICACHE_CRSP_ST_H 12'hB8E
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// PERF: dcache
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`define CSR_MPM_DCACHE_READS 12'hB0F // total reads
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`define CSR_MPM_DCACHE_READS_H 12'hB8F
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`define CSR_MPM_DCACHE_WRITES 12'hB10 // total writes
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`define CSR_MPM_DCACHE_WRITES_H 12'hB90
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`define CSR_MPM_DCACHE_MISS_R 12'hB11 // read misses
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`define CSR_MPM_DCACHE_MISS_R_H 12'hB91
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`define CSR_MPM_DCACHE_MISS_W 12'hB12 // write misses
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`define CSR_MPM_DCACHE_MISS_W_H 12'hB92
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`define CSR_MPM_DCACHE_BANK_ST 12'hB13 // bank conflicts stalls
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`define CSR_MPM_DCACHE_BANK_ST_H 12'hB93
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`define CSR_MPM_DCACHE_MSHR_ST 12'hB14 // MSHR stalls
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`define CSR_MPM_DCACHE_MSHR_ST_H 12'hB94
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`define CSR_MPM_DCACHE_PIPE_ST 12'hB15 // pipeline stalls
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`define CSR_MPM_DCACHE_PIPE_ST_H 12'hB95
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`define CSR_MPM_DCACHE_CRSP_ST 12'hB16 // core response stalls
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`define CSR_MPM_DCACHE_CRSP_ST_H 12'hB96
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// PERF: smem
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`define CSR_MPM_SMEM_READS 12'hB17 // total reads
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`define CSR_MPM_SMEM_READS_H 12'hB97
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`define CSR_MPM_SMEM_WRITES 12'hB18 // total writes
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`define CSR_MPM_SMEM_WRITES_H 12'hB98
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`define CSR_MPM_SMEM_BANK_ST 12'hB19 // bank conflicts stalls
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`define CSR_MPM_SMEM_BANK_ST_H 12'hB99
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// PERF: memory
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`define CSR_MPM_DRAM_READS 12'hB1A // dram reads
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`define CSR_MPM_DRAM_READS_H 12'hB9A
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`define CSR_MPM_DRAM_WRITES 12'hB1B // dram writes
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`define CSR_MPM_DRAM_WRITES_H 12'hB9B
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`define CSR_MPM_DRAM_ST 12'hB1C // dram request stalls
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`define CSR_MPM_DRAM_ST_H 12'hB9C
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`define CSR_MPM_DRAM_LAT 12'hB1D // dram latency (total)
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`define CSR_MPM_DRAM_LAT_H 12'hB9D
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// Machine Information Registers
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`define CSR_MVENDORID 12'hF11
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`define CSR_MARCHID 12'hF12
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`define CSR_MIMPID 12'hF13
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`define CSR_MHARTID 12'hF14
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// Pipeline Queues ////////////////////////////////////////////////////////////
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// Size of instruction queue
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`ifndef IBUF_SIZE
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`define IBUF_SIZE 4
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`endif
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// Size of LSU Request Queue
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`ifndef LSUQ_SIZE
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`define LSUQ_SIZE 8
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`endif
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// Size of FPU Request Queue
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`ifndef FPUQ_SIZE
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`define FPUQ_SIZE 8
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`endif
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// Icache Configurable Knobs //////////////////////////////////////////////////
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// Size of cache in bytes
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`ifndef ICACHE_SIZE
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`define ICACHE_SIZE 2048
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`endif
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// Core Request Queue Size
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`ifndef ICREQ_SIZE
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`define ICREQ_SIZE 4
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`endif
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// Core Response Queue Size
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`ifndef ICRSQ_SIZE
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`define ICRSQ_SIZE 4
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`endif
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// Miss Handling Register Size
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`ifndef IMSHR_SIZE
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`define IMSHR_SIZE `NUM_WARPS
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`endif
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// DRAM Request Queue Size
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`ifndef IDREQ_SIZE
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`define IDREQ_SIZE 4
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`endif
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// DRAM Response Queue Size
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`ifndef IDRSQ_SIZE
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`define IDRSQ_SIZE 4
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`endif
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// Dcache Configurable Knobs //////////////////////////////////////////////////
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// Size of cache in bytes
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`ifndef DCACHE_SIZE
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`define DCACHE_SIZE 8192
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`endif
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// Number of banks
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`ifndef DNUM_BANKS
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`define DNUM_BANKS `NUM_THREADS
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`endif
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// Core Request Queue Size
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`ifndef DCREQ_SIZE
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`define DCREQ_SIZE 4
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`endif
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// Core Response Queue Size
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`ifndef DCRSQ_SIZE
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`define DCRSQ_SIZE 4
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`endif
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// Miss Handling Register Size
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`ifndef DMSHR_SIZE
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`define DMSHR_SIZE `LSUQ_SIZE
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`endif
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// DRAM Request Queue Size
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`ifndef DDREQ_SIZE
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`define DDREQ_SIZE 4
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`endif
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// DRAM Response Queue Size
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`ifndef DDRSQ_SIZE
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`define DDRSQ_SIZE 4
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`endif
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// SM Configurable Knobs //////////////////////////////////////////////////////
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// Size of cache in bytes
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`ifndef SMEM_SIZE
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`define SMEM_SIZE (1024*4*4)
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`endif
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// Number of banks
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`ifndef SNUM_BANKS
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`define SNUM_BANKS `NUM_THREADS
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`endif
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// Core Request Queue Size
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`ifndef SCREQ_SIZE
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`define SCREQ_SIZE 4
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`endif
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// Core Response Queue Size
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`ifndef SCRSQ_SIZE
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`define SCRSQ_SIZE 4
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`endif
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// L2cache Configurable Knobs /////////////////////////////////////////////////
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// Size of cache in bytes
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`ifndef L2CACHE_SIZE
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`define L2CACHE_SIZE 131072
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`endif
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// Number of banks
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`ifndef L2NUM_BANKS
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`define L2NUM_BANKS `MIN(`NUM_CORES, 4)
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`endif
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// Core Request Queue Size
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`ifndef L2CREQ_SIZE
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`define L2CREQ_SIZE 4
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`endif
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// Core Response Queue Size
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`ifndef L2CRSQ_SIZE
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`define L2CRSQ_SIZE 4
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`endif
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// Miss Handling Register Size
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`ifndef L2MSHR_SIZE
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`define L2MSHR_SIZE 8
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`endif
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// DRAM Request Queue Size
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`ifndef L2DREQ_SIZE
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`define L2DREQ_SIZE 4
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`endif
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// DRAM Response Queue Size
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`ifndef L2DRSQ_SIZE
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`define L2DRSQ_SIZE 4
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`endif
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// L3cache Configurable Knobs /////////////////////////////////////////////////
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// Size of cache in bytes
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`ifndef L3CACHE_SIZE
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`define L3CACHE_SIZE 262144
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`endif
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// Number of banks
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`ifndef L3NUM_BANKS
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`define L3NUM_BANKS `MIN(`NUM_CLUSTERS, 4)
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`endif
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// Core Request Queue Size
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`ifndef L3CREQ_SIZE
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`define L3CREQ_SIZE 4
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`endif
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// Core Response Queue Size
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`ifndef L3CRSQ_SIZE
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`define L3CRSQ_SIZE 4
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`endif
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// Miss Handling Register Size
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`ifndef L3MSHR_SIZE
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`define L3MSHR_SIZE 8
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`endif
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// DRAM Request Queue Size
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`ifndef L3DREQ_SIZE
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`define L3DREQ_SIZE 4
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`endif
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// DRAM Response Queue Size
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`ifndef L3DRSQ_SIZE
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`define L3DRSQ_SIZE 4
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`endif
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`endif
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