felsabbagh3 b4d921f49a set_top_level tcl

2019-10-23 11:56:32 -04:00

..

191017.log

added log file

2019-10-17 14:00:22 -04:00

dc_noOpt.log

Finished synthesis with no optimization, cell count increasts to 100k

2019-10-21 17:53:51 -04:00

dc.log

Added log file of synthesis, too many registers are removed

2019-10-17 14:25:54 -04:00

syn.tcl

set_top_level tcl

2019-10-23 11:56:32 -04:00