47 lines
1.4 KiB
Systemverilog
47 lines
1.4 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_priority_arbiter #(
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parameter NUM_REQS = 1,
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parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
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) (
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input wire [NUM_REQS-1:0] requests,
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output wire [LOG_NUM_REQS-1:0] grant_index,
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output wire [NUM_REQS-1:0] grant_onehot,
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output wire grant_valid
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);
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if (NUM_REQS == 1) begin
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assign grant_index = '0;
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assign grant_onehot = requests;
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assign grant_valid = requests[0];
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end else begin
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VX_priority_encoder #(
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.N (NUM_REQS)
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) priority_encoder (
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.data_in (requests),
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.index (grant_index),
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.onehot (grant_onehot),
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.valid_out (grant_valid)
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);
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end
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endmodule
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`TRACING_ON
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