67 lines
1.8 KiB
Verilog
67 lines
1.8 KiB
Verilog
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`include "VX_define.v"
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module VX_lsu (
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// input wire clk,
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VX_lsu_req_inter VX_lsu_req,
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// Write back to GPR
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VX_inst_mem_wb_inter VX_mem_wb,
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VX_dcache_response_inter VX_dcache_rsp,
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VX_dcache_request_inter VX_dcache_req,
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output wire out_delay
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);
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// VX_inst_mem_wb_inter VX_mem_wb_temp();
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assign out_delay = VX_dcache_rsp.delay;
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// Generate Addresses
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wire[`NT_M1:0][31:0] address;
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VX_lsu_addr_gen VX_lsu_addr_gen
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(
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.base_address(VX_lsu_req.base_address),
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.offset (VX_lsu_req.offset),
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.address (address)
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);
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genvar index;
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for (index = 0; index <= `NT_M1; index = index + 1) begin
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assign VX_dcache_req.out_cache_driver_in_address[index] = address[index];
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assign VX_dcache_req.out_cache_driver_in_data[index] = VX_lsu_req.store_data[index];
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assign VX_dcache_req.out_cache_driver_in_valid[index] = VX_lsu_req.valid[index];
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assign VX_mem_wb.loaded_data[index] = VX_dcache_rsp.in_cache_driver_out_data[index];
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end
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assign VX_dcache_req.out_cache_driver_in_mem_read = VX_lsu_req.mem_read;
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assign VX_dcache_req.out_cache_driver_in_mem_write = VX_lsu_req.mem_write;
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assign VX_mem_wb.rd = VX_lsu_req.rd;
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assign VX_mem_wb.wb = VX_lsu_req.wb;
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assign VX_mem_wb.wb_valid = VX_lsu_req.valid;
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assign VX_mem_wb.wb_warp_num = VX_lsu_req.warp_num;
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// wire zero_temp = 0;
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// VX_generic_register #(.N(256)) register_wb_data
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// (
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// .clk (clk),
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// .reset(zero_temp),
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// .stall(zero_temp),
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// .flush(zero_temp),
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// .in ({VX_mem_wb_temp.loaded_data, VX_mem_wb_temp.rd, VX_mem_wb_temp.wb, VX_mem_wb_temp.wb_valid, VX_mem_wb_temp.wb_warp_num}),
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// .out ({VX_mem_wb.loaded_data , VX_mem_wb.rd , VX_mem_wb.wb , VX_mem_wb.wb_valid , VX_mem_wb.wb_warp_num })
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// );
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endmodule // Memory
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