21 lines
367 B
Verilog
21 lines
367 B
Verilog
`include "../VX_define.v"
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module VX_set_bit (
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input wire[1:0] index,
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output reg[`NT_M1:0] mask
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);
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integer some_index;
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always @(*) begin
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for (some_index = 0; some_index <= `NT_M1; some_index = some_index + 1) begin
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if (some_index[1:0] == index) begin
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assign mask[some_index] = 0;
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end
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else begin
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assign mask[some_index] = 1;
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end
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end
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end
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endmodule |