59 lines
1.6 KiB
Systemverilog
59 lines
1.6 KiB
Systemverilog
`ifndef VX_PERF_MEMSYS_IF
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`define VX_PERF_MEMSYS_IF
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`include "VX_define.vh"
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interface VX_perf_memsys_if ();
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wire [`PERF_CTR_BITS-1:0] icache_reads;
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wire [`PERF_CTR_BITS-1:0] icache_read_misses;
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wire [`PERF_CTR_BITS-1:0] dcache_reads;
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wire [`PERF_CTR_BITS-1:0] dcache_writes;
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wire [`PERF_CTR_BITS-1:0] dcache_read_misses;
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wire [`PERF_CTR_BITS-1:0] dcache_write_misses;
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wire [`PERF_CTR_BITS-1:0] dcache_bank_stalls;
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wire [`PERF_CTR_BITS-1:0] dcache_mshr_stalls;
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wire [`PERF_CTR_BITS-1:0] smem_reads;
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wire [`PERF_CTR_BITS-1:0] smem_writes;
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wire [`PERF_CTR_BITS-1:0] smem_bank_stalls;
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wire [`PERF_CTR_BITS-1:0] mem_reads;
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wire [`PERF_CTR_BITS-1:0] mem_writes;
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wire [`PERF_CTR_BITS-1:0] mem_latency;
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modport master (
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output icache_reads,
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output icache_read_misses,
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output dcache_reads,
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output dcache_writes,
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output dcache_read_misses,
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output dcache_write_misses,
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output dcache_bank_stalls,
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output dcache_mshr_stalls,
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output smem_reads,
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output smem_writes,
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output smem_bank_stalls,
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output mem_reads,
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output mem_writes,
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output mem_latency
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);
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modport slave (
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input icache_reads,
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input icache_read_misses,
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input dcache_reads,
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input dcache_writes,
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input dcache_read_misses,
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input dcache_write_misses,
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input dcache_bank_stalls,
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input dcache_mshr_stalls,
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input smem_reads,
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input smem_writes,
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input smem_bank_stalls,
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input mem_reads,
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input mem_writes,
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input mem_latency
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);
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endinterface
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`endif |