318 lines
11 KiB
Systemverilog
318 lines
11 KiB
Systemverilog
`include "VX_tex_define.vh"
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module VX_tex_mem #(
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parameter CORE_ID = 0,
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parameter REQ_INFOW = 1,
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parameter NUM_REQS = 1
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) (
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input wire clk,
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input wire reset,
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// memory interface
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VX_dcache_req_if.master dcache_req_if,
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VX_dcache_rsp_if.slave dcache_rsp_if,
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// inputs
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input wire req_valid,
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input wire [NUM_REQS-1:0] req_tmask,
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input wire [`TEX_FILTER_BITS-1:0] req_filter,
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input wire [`TEX_LGSTRIDE_BITS-1:0] req_lgstride,
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input wire [NUM_REQS-1:0][31:0] req_baseaddr,
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input wire [NUM_REQS-1:0][3:0][31:0] req_addr,
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input wire [REQ_INFOW-1:0] req_info,
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output wire req_ready,
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// outputs
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output wire rsp_valid,
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output wire [NUM_REQS-1:0] rsp_tmask,
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output wire [NUM_REQS-1:0][3:0][31:0] rsp_data,
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output wire [REQ_INFOW-1:0] rsp_info,
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input wire rsp_ready
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);
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`UNUSED_PARAM (CORE_ID)
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localparam RSP_CTR_W = $clog2(NUM_REQS * 4 + 1);
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// full address calculation
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wire [NUM_REQS-1:0][3:0][31:0] full_addr;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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for (genvar j = 0; j < 4; ++j) begin
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assign full_addr[i][j] = req_baseaddr[i] + req_addr[i][j];
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end
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end
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wire [3:0] dup_reqs;
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wire [3:0][NUM_REQS-1:0][29:0] req_addr_w;
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wire [3:0][NUM_REQS-1:0][1:0] align_offs;
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// reorder address into quads
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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for (genvar j = 0; j < 4; ++j) begin
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assign req_addr_w[j][i] = full_addr[i][j][31:2];
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assign align_offs[j][i] = full_addr[i][j][1:0];
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end
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end
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// detect duplicate addresses
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for (genvar i = 0; i < 4; ++i) begin
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wire [NUM_REQS-2:0] addr_matches;
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for (genvar j = 0; j < (NUM_REQS-1); ++j) begin
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assign addr_matches[j] = (req_addr_w[i][j+1] == req_addr_w[i][0]) || ~req_tmask[j+1];
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end
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assign dup_reqs[i] = req_tmask[0] && (& addr_matches);
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end
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// save request addresses into fifo
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wire reqq_push, reqq_pop, reqq_empty, reqq_full;
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wire [3:0][NUM_REQS-1:0][29:0] q_req_addr;
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wire [NUM_REQS-1:0] q_req_tmask;
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wire [`TEX_FILTER_BITS-1:0] q_req_filter;
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wire [REQ_INFOW-1:0] q_req_info;
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wire [`TEX_LGSTRIDE_BITS-1:0] q_req_lgstride;
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wire [3:0][NUM_REQS-1:0][1:0] q_align_offs;
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wire [3:0] q_dup_reqs;
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wire [`NW_BITS-1:0] q_req_wid;
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wire [31:0] q_req_PC;
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wire [`UUID_BITS-1:0] q_req_uuid;
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assign reqq_push = req_valid && req_ready;
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VX_fifo_queue #(
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.DATAW ((NUM_REQS * 4 * 30) + NUM_REQS + REQ_INFOW + `TEX_FILTER_BITS + `TEX_LGSTRIDE_BITS + (4 * NUM_REQS * 2) + 4),
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.SIZE (`TEXQ_SIZE),
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.OUT_REG (1)
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) req_queue (
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.clk (clk),
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.reset (reset),
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.push (reqq_push),
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.pop (reqq_pop),
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.data_in ({req_addr_w, req_tmask, req_info, req_filter, req_lgstride, align_offs, dup_reqs}),
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.data_out ({q_req_addr, q_req_tmask, q_req_info, q_req_filter, q_req_lgstride, q_align_offs, q_dup_reqs}),
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.empty (reqq_empty),
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.full (reqq_full),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (size)
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);
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// can take more requests?
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assign req_ready = ~reqq_full;
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///////////////////////////////////////////////////////////////////////////
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wire req_texel_valid;
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wire sent_all_ready, last_texel_sent;
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wire req_texel_dup;
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wire [NUM_REQS-1:0][29:0] req_texel_addr;
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reg [1:0] req_texel_idx;
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reg req_texels_done;
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always @(posedge clk) begin
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if (reset || last_texel_sent) begin
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req_texel_idx <= 0;
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end else if (req_texel_valid && sent_all_ready) begin
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req_texel_idx <= req_texel_idx + 1;
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end
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end
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always @(posedge clk) begin
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if (reset || reqq_pop) begin
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req_texels_done <= 0;
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end else if (last_texel_sent) begin
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req_texels_done <= 1;
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end
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end
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assign req_texel_valid = ~reqq_empty && ~req_texels_done;
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assign req_texel_addr = q_req_addr[req_texel_idx];
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assign req_texel_dup = q_dup_reqs[req_texel_idx];
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wire is_last_texel = (req_texel_idx == (q_req_filter ? 3 : 0));
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assign last_texel_sent = req_texel_valid && sent_all_ready && is_last_texel;
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// DCache Request
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reg [NUM_REQS-1:0] texel_sent_mask;
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wire [NUM_REQS-1:0] dcache_req_fire = dcache_req_if.valid & dcache_req_if.ready;
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wire dcache_req_fire_any = (| dcache_req_fire);
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assign sent_all_ready = (&(dcache_req_if.ready | texel_sent_mask | ~q_req_tmask))
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|| (req_texel_dup & dcache_req_if.ready[0]);
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always @(posedge clk) begin
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if (reset || sent_all_ready) begin
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texel_sent_mask <= 0;
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end else begin
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texel_sent_mask <= texel_sent_mask | dcache_req_fire;
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end
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end
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wire [NUM_REQS-1:0] req_dup_mask = {{(NUM_REQS-1){~req_texel_dup}}, 1'b1};
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assign {q_req_wid, q_req_PC, q_req_uuid} = q_req_info[`NW_BITS+32+`UUID_BITS-1:0];
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`UNUSED_VAR (q_req_wid)
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`UNUSED_VAR (q_req_PC)
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assign dcache_req_if.valid = {NUM_REQS{req_texel_valid}} & q_req_tmask & req_dup_mask & ~texel_sent_mask;
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assign dcache_req_if.rw = {NUM_REQS{1'b0}};
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assign dcache_req_if.addr = req_texel_addr;
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assign dcache_req_if.byteen = {NUM_REQS{4'b0}};
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assign dcache_req_if.data = 'x;
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assign dcache_req_if.tag = {NUM_REQS{q_req_uuid, `LSU_TAG_ID_BITS'(req_texel_idx), `CACHE_ADDR_TYPE_BITS'(0)}};
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// Dcache Response
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reg [3:0][NUM_REQS-1:0][31:0] rsp_texels, rsp_texels_n;
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wire [NUM_REQS-1:0][3:0][31:0] rsp_texels_qual;
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reg [NUM_REQS-1:0][31:0] rsp_data_qual;
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reg [RSP_CTR_W-1:0] rsp_rem_ctr, rsp_rem_ctr_init;
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wire [RSP_CTR_W-1:0] rsp_rem_ctr_n;
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wire [NUM_REQS-1:0][1:0] rsp_align_offs;
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wire [$clog2(NUM_REQS+1)-1:0] q_req_size;
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wire [$clog2(NUM_REQS+1)-1:0] dcache_rsp_size;
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wire dcache_rsp_fire;
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wire [1:0] rsp_texel_idx;
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wire rsp_texel_dup;
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assign rsp_texel_idx = dcache_rsp_if.tag[`CACHE_ADDR_TYPE_BITS +: 2];
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`UNUSED_VAR (dcache_rsp_if.tag)
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assign rsp_texel_dup = q_dup_reqs[rsp_texel_idx];
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assign rsp_align_offs = q_align_offs[rsp_texel_idx];
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assign dcache_rsp_fire = dcache_rsp_if.valid && dcache_rsp_if.ready;
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for (genvar i = 0; i < NUM_REQS; i++) begin
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wire [31:0] src_mask = {32{dcache_rsp_if.tmask[i]}};
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wire [31:0] src_data = ((i == 0 || rsp_texel_dup) ? dcache_rsp_if.data[0] : dcache_rsp_if.data[i]) & src_mask;
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reg [31:0] rsp_data_shifted;
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always @(*) begin
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rsp_data_shifted[31:16] = src_data[31:16];
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rsp_data_shifted[15:0] = rsp_align_offs[i][1] ? src_data[31:16] : src_data[15:0];
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rsp_data_shifted[7:0] = rsp_align_offs[i][0] ? rsp_data_shifted[15:8] : rsp_data_shifted[7:0];
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end
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always @(*) begin
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case (q_req_lgstride)
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0: rsp_data_qual[i] = 32'(rsp_data_shifted[7:0]);
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1: rsp_data_qual[i] = 32'(rsp_data_shifted[15:0]);
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default: rsp_data_qual[i] = rsp_data_shifted;
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endcase
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end
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end
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always @(*) begin
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rsp_texels_n = rsp_texels;
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rsp_texels_n[rsp_texel_idx] |= rsp_data_qual;
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end
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always @(posedge clk) begin
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if (reset || reqq_pop) begin
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rsp_texels <= '0;
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end else if (dcache_rsp_fire) begin
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rsp_texels <= rsp_texels_n;
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end
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end
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`POP_COUNT(q_req_size, q_req_tmask);
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always @(*) begin
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rsp_rem_ctr_init = q_dup_reqs[0] ? RSP_CTR_W'(1) : RSP_CTR_W'(q_req_size);
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if (q_req_filter) begin
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for (integer i = 1; i < 4; ++i) begin
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rsp_rem_ctr_init += q_dup_reqs[i] ? RSP_CTR_W'(1) : RSP_CTR_W'(q_req_size);
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end
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end
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end
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wire [NUM_REQS-1:0] dcache_rsp_tmask = dcache_rsp_if.tmask;
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`POP_COUNT(dcache_rsp_size, dcache_rsp_tmask);
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assign rsp_rem_ctr_n = rsp_rem_ctr - RSP_CTR_W'(dcache_rsp_size);
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always @(posedge clk) begin
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if (reset) begin
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rsp_rem_ctr <= 0;
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end else begin
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if (dcache_req_fire_any && 0 == rsp_rem_ctr) begin
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rsp_rem_ctr <= rsp_rem_ctr_init;
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end else if (dcache_rsp_fire) begin
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rsp_rem_ctr <= rsp_rem_ctr_n;
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end
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end
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end
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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for (genvar j = 0; j < 4; ++j) begin
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assign rsp_texels_qual[i][j] = rsp_texels_n[j][i];
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end
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end
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wire stall_out = rsp_valid && ~rsp_ready;
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wire is_last_rsp = (rsp_rem_ctr == RSP_CTR_W'(dcache_rsp_size));
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wire rsp_texels_done = dcache_rsp_fire && is_last_rsp;
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assign reqq_pop = rsp_texels_done && ~stall_out;
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VX_pipe_register #(
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.DATAW (1 + NUM_REQS + REQ_INFOW + (4 * NUM_REQS * 32)),
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.RESETW (1)
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) rsp_pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({rsp_texels_done, q_req_tmask, q_req_info, rsp_texels_qual}),
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.data_out ({rsp_valid, rsp_tmask, rsp_info, rsp_data})
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);
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// Can accept new cache response?
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assign dcache_rsp_if.ready = ~(is_last_rsp && stall_out);
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`ifdef DBG_TRACE_TEX
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wire [`NW_BITS-1:0] req_wid, rsp_wid;
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wire [31:0] req_PC, rsp_PC;
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wire [`UUID_BITS-1:0] req_uuid, rsp_uuid;
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assign {req_wid, req_PC, req_uuid} = req_info[`NW_BITS+32+`UUID_BITS-1:0];
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assign {rsp_wid, rsp_PC, rsp_uuid} = rsp_info[`NW_BITS+32+`UUID_BITS-1:0];
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always @(posedge clk) begin
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if (dcache_req_fire_any) begin
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dpi_trace("%d: core%0d-tex-cache-req: wid=%0d, PC=%0h, tmask=%b, tag=%0h, addr=",
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$time, CORE_ID, q_req_wid, q_req_PC, dcache_req_fire, req_texel_idx);
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`TRACE_ARRAY1D(req_texel_addr, NUM_REQS);
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dpi_trace(", is_dup=%b (#%0d)\n", req_texel_dup, q_req_uuid);
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end
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if (dcache_rsp_fire) begin
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dpi_trace("%d: core%0d-tex-cache-rsp: wid=%0d, PC=%0h, tmask=%b, tag=%0h, data=",
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$time, CORE_ID, q_req_wid, q_req_PC, dcache_rsp_if.tmask, rsp_texel_idx);
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`TRACE_ARRAY1D(dcache_rsp_if.data, NUM_REQS);
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dpi_trace(" (#%0d)\n", q_req_uuid);
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end
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if (req_valid && req_ready) begin
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dpi_trace("%d: core%0d-tex-mem-req: wid=%0d, PC=%0h, tmask=%b, filter=%0d, lgstride=%0d, baseaddr=",
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$time, CORE_ID, req_wid, req_PC, req_tmask, req_filter, req_lgstride);
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`TRACE_ARRAY1D(req_baseaddr, NUM_REQS);
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dpi_trace(", addr=");
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`TRACE_ARRAY2D(req_addr, 4, NUM_REQS);
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dpi_trace(" (#%0d)\n", req_uuid);
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end
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if (rsp_valid && rsp_ready) begin
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dpi_trace("%d: core%0d-tex-mem-rsp: wid=%0d, PC=%0h, tmask=%b, data=",
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$time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask);
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`TRACE_ARRAY2D(rsp_data, 4, NUM_REQS);
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dpi_trace(" (#%0d)\n", rsp_uuid);
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end
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end
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`endif
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endmodule
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