395 lines
15 KiB
Verilog
395 lines
15 KiB
Verilog
`include "VX_define.vh"
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`include "VX_print_instr.vh"
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module VX_decode #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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VX_ifetch_rsp_if ifetch_rsp_if,
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// outputs
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VX_decode_if decode_if,
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VX_wstall_if wstall_if,
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VX_join_if join_if
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);
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wire in_valid = ifetch_rsp_if.valid;
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wire [31:0] instr = ifetch_rsp_if.instr;
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reg [`ALU_BITS-1:0] alu_op;
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reg [`BR_BITS-1:0] br_op;
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reg [`LSU_BITS-1:0] lsu_op;
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reg [`CSR_BITS-1:0] csr_op;
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reg [`MUL_BITS-1:0] mul_op;
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reg [`FPU_BITS-1:0] fpu_op;
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reg [`GPU_BITS-1:0] gpu_op;
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reg [19:0] upper_imm;
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reg [31:0] jalx_offset;
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reg [31:0] src2_imm;
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wire [6:0] opcode = instr[6:0];
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wire [2:0] func3 = instr[14:12];
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wire [6:0] func7 = instr[31:25];
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wire [11:0] u_12 = instr[31:20];
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wire [4:0] rd = instr[11:7];
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wire [4:0] rs1 = instr[19:15];
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wire [4:0] rs2 = instr[24:20];
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wire [4:0] rs3 = instr[31:27];
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// opcode types
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wire is_rtype = (opcode == `INST_R);
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wire is_ltype = (opcode == `INST_L);
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wire is_itype = (opcode == `INST_I);
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wire is_stype = (opcode == `INST_S);
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wire is_btype = (opcode == `INST_B);
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wire is_jal = (opcode == `INST_JAL);
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wire is_jalr = (opcode == `INST_JALR);
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wire is_lui = (opcode == `INST_LUI);
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wire is_auipc = (opcode == `INST_AUIPC);
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wire is_jals = (opcode == `INST_SYS) && (func3 == 0);
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wire is_csr = (opcode == `INST_SYS) && (func3 != 0);
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wire is_gpu = (opcode == `INST_GPU);
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// upper immediate
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always @(*) begin
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case (opcode)
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`INST_LUI: upper_imm = {func7, rs2, rs1, func3};
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`INST_AUIPC: upper_imm = {func7, rs2, rs1, func3};
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default: upper_imm = 20'h0;
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endcase
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end
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// I-type immediate
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wire alu_shift_i = (func3 == 3'h1) || (func3 == 3'h5);
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wire [11:0] alu_shift_imm = {{7{1'b0}}, rs2};
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wire [11:0] alu_imm = alu_shift_i ? alu_shift_imm : u_12;
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always @(*) begin
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case (opcode)
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`INST_I: src2_imm = {{20{alu_imm[11]}}, alu_imm};
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`INST_S,
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`INST_FS: src2_imm = {{20{func7[6]}}, func7, rd};
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`INST_L,
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`INST_FL: src2_imm = {{20{u_12[11]}}, u_12};
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`INST_B: src2_imm = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
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default: src2_imm = 32'hdeadbeef;
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endcase
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end
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// JAL
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wire [20:0] jal_imm = {instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
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wire [31:0] jal_offset = {{11{jal_imm[20]}}, jal_imm};
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wire [11:0] jalr_imm = {func7, rs2};
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wire [31:0] jalr_offset = {{20{jalr_imm[11]}}, jalr_imm};
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always @(*) begin
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case (opcode)
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`INST_JAL: jalx_offset = jal_offset;
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`INST_JALR: jalx_offset = jalr_offset;
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default: jalx_offset = 32'd4;
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endcase
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end
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// BRANCH
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wire is_br = (is_btype || is_jal || is_jalr || is_jals);
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always @(*) begin
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br_op = `BR_EQ;
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case (opcode)
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`INST_B: begin
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case (func3)
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3'h0: br_op = `BR_EQ;
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3'h1: br_op = `BR_NE;
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3'h4: br_op = `BR_LT;
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3'h5: br_op = `BR_GE;
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3'h6: br_op = `BR_LTU;
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3'h7: br_op = `BR_GEU;
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default:;
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endcase
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end
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`INST_JAL: br_op = `BR_JAL;
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`INST_JALR: br_op = `BR_JALR;
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`INST_SYS: begin
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if (is_jals && u_12 == 12'h000) br_op = `BR_ECALL;
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if (is_jals && u_12 == 12'h001) br_op = `BR_EBREAK;
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if (is_jals && u_12 == 12'h302) br_op = `BR_MRET;
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if (is_jals && u_12 == 12'h102) br_op = `BR_SRET;
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if (is_jals && u_12 == 12'h7B2) br_op = `BR_DRET;
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end
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default:;
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endcase
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end
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// ALU
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always @(*) begin
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alu_op = `ALU_OTHER;
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if (is_lui) begin
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alu_op = `ALU_LUI;
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end else if (is_auipc) begin
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alu_op = `ALU_AUIPC;
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end else if (is_itype || is_rtype) begin
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case (func3)
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3'h0: alu_op = (is_rtype && func7 == 7'h20) ? `ALU_SUB : `ALU_ADD;
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3'h1: alu_op = `ALU_SLL;
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3'h2: alu_op = `ALU_SLT;
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3'h3: alu_op = `ALU_SLTU;
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3'h4: alu_op = `ALU_XOR;
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3'h5: alu_op = (func7 == 7'h0) ? `ALU_SRL : `ALU_SRA;
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3'h6: alu_op = `ALU_OR;
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3'h7: alu_op = `ALU_AND;
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default:;
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endcase
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end
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end
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// CSR
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wire is_csr_imm = is_csr && (func3[2] == 1);
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always @(*) begin
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csr_op = `CSR_OTHER;
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case (func3[1:0])
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2'h1: csr_op = `CSR_RW;
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2'h2: csr_op = `CSR_RS;
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2'h3: csr_op = `CSR_RC;
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default:;
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endcase
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end
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// MUL
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`ifdef EXT_M_ENABLE
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wire is_mul = is_rtype && (func7 == 7'h1);
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always @(*) begin
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mul_op = `MUL_MUL;
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case (func3)
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3'h0: mul_op = `MUL_MUL;
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3'h1: mul_op = `MUL_MULH;
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3'h2: mul_op = `MUL_MULHSU;
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3'h3: mul_op = `MUL_MULHU;
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3'h4: mul_op = `MUL_DIV;
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3'h5: mul_op = `MUL_DIVU;
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3'h6: mul_op = `MUL_REM;
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3'h7: mul_op = `MUL_REMU;
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default:;
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endcase
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end
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`else
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wire is_mul = 0;
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always @(*) begin
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mul_op = `MUL_MUL;
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end
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`endif
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// FPU
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`ifdef EXT_F_ENABLE
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wire is_fl = (opcode == `INST_FL) && ((func3 == 2));
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wire is_fs = (opcode == `INST_FS) && ((func3 == 2));
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wire is_fci = (opcode == `INST_FCI);
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wire is_fmadd = (opcode == `INST_FMADD);
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wire is_fmsub = (opcode == `INST_FMSUB);
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wire is_fnmsub = (opcode == `INST_FNMSUB);
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wire is_fnmadd = (opcode == `INST_FNMADD);
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wire is_fcmp = is_fci && (func7 == 7'h50); // compare
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wire is_fcvti = is_fci && (func7 == 7'h60); // convert to int
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wire is_fcvtf = is_fci && (func7 == 7'h68); // convert to float
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wire is_fmvcls = is_fci && (func7 == 7'h70 || func7 == 7'h78); // move + class
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wire is_fr4 = is_fmadd || is_fmsub || is_fnmsub || is_fnmadd;
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wire is_fpu = (is_fl || is_fs || is_fci || is_fr4);
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always @(*) begin
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fpu_op = `FPU_OTHER;
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if (is_fr4) begin
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case ({is_fmadd, is_fmsub, is_fnmsub, is_fnmadd})
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4'b1000: fpu_op = `FPU_MADD;
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4'b0100: fpu_op = `FPU_MSUB;
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4'b0010: fpu_op = `FPU_NMSUB;
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4'b0001: fpu_op = `FPU_NMADD;
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default:;
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endcase
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end
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else begin
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case (func7)
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7'h00: fpu_op = `FPU_ADD;
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7'h04: fpu_op = `FPU_SUB;
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7'h08: fpu_op = `FPU_MUL;
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7'h0C: fpu_op = `FPU_DIV;
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7'h10: fpu_op = (func3[1]) ? `FPU_SGNJX : ((func3[0]) ? `FPU_SGNJN : `FPU_SGNJ);
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7'h14: fpu_op = (func3 == 3'h0) ? `FPU_MIN : `FPU_MAX;
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7'h2C: fpu_op = `FPU_SQRT;
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7'h50: fpu_op = `FPU_CMP; // wb to intReg
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7'h60: fpu_op = (instr[20]) ? `FPU_CVTWUS : `FPU_CVTWS; // doesn't need rs2, and read rs1 from fpReg, WB to intReg
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7'h68: fpu_op = (instr[20]) ? `FPU_CVTSWU : `FPU_CVTSW; // doesn't need rs2, and read rs1 from intReg
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7'h70: fpu_op = (func3 == 3'h0) ? `FPU_MVXW : `FPU_CLASS; // both wb to intReg
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7'h78: fpu_op = `FPU_MVWX;
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default:;
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endcase
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end
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end
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`else
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wire is_fl = 0;
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wire is_fs = 0;
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wire is_fci = 0;
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wire is_fcvti = 0;
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wire is_fcvtf = 0;
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wire is_fmvcls = 0;
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wire is_fr4 = 0;
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wire is_fpu = 0;
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always @(*) begin
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fpu_op = `FPU_OTHER;
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end
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`endif
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// LSU
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wire is_lsu = (is_ltype || is_stype || is_fl || is_fs);
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always @(*) begin
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lsu_op = {is_stype, func3};
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if (is_fl) lsu_op = `LSU_LW;
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if (is_fs) lsu_op = `LSU_SW;
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end
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// GPU
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always @(*) begin
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gpu_op = `GPU_OTHER;
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case (func3)
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3'h0: gpu_op = `GPU_TMC;
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3'h1: gpu_op = `GPU_WSPAWN;
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3'h2: gpu_op = `GPU_SPLIT;
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3'h3: gpu_op = `GPU_JOIN;
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3'h4: gpu_op = `GPU_BAR;
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default:;
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endcase
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end
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///////////////////////////////////////////////////////////////////////////
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wire use_rd = (is_fl || is_fci || is_fr4)
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|| ((rd != 0) && (is_itype || is_rtype || is_lui || is_auipc || is_csr || is_jal || is_jalr || is_jals || is_ltype));
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wire use_rs1 = is_fpu
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|| is_gpu
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|| ((is_jalr || is_btype || is_ltype || is_stype || is_itype || is_rtype || ~is_csr_imm || is_gpu) && (rs1 != 0));
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wire use_rs2 = (is_fpu && ~(is_fl || (fpu_op == `FPU_SQRT) || is_fcvti || is_fcvtf || is_fmvcls))
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|| (is_gpu && (gpu_op == `GPU_BAR || gpu_op == `GPU_WSPAWN))
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|| ((is_btype || is_stype || is_rtype) && (rs2 != 0));
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wire use_rs3 = is_fr4;
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wire [4:0] rs1_qual = is_lui ? 5'h0 : rs1;
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///////////////////////////////////////////////////////////////////////////
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VX_decode_if decode_tmp_if();
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assign decode_tmp_if.valid = ifetch_rsp_if.valid;
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assign decode_tmp_if.warp_num = ifetch_rsp_if.warp_num;
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assign decode_tmp_if.thread_mask= ifetch_rsp_if.thread_mask;
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assign decode_tmp_if.curr_PC = ifetch_rsp_if.curr_PC;
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assign decode_tmp_if.next_PC = ifetch_rsp_if.curr_PC + 32'h4;
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assign decode_tmp_if.ex_type = is_lsu ? `EX_LSU :
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is_csr ? `EX_CSR :
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is_mul ? `EX_MUL :
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is_fpu ? `EX_FPU :
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is_gpu ? `EX_GPU :
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is_br ? `EX_ALU :
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(is_rtype || is_itype || is_lui || is_auipc) ? `EX_ALU :
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`EX_NOP;
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assign decode_tmp_if.ex_op = is_lsu ? `OP_BITS'(lsu_op) :
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is_csr ? `OP_BITS'(csr_op) :
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is_mul ? `OP_BITS'(mul_op) :
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is_fpu ? `OP_BITS'(fpu_op) :
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is_gpu ? `OP_BITS'(gpu_op) :
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is_br ? `OP_BITS'({1'b1, br_op}) :
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(is_rtype || is_itype || is_lui || is_auipc) ? `OP_BITS'(alu_op) :
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0;
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assign decode_tmp_if.wb = use_rd;
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`ifdef EXT_F_ENABLE
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wire rd_is_fp = is_fpu && ~(is_fcmp || is_fcvti || (fpu_op == `FPU_MVXW || fpu_op == `FPU_CLASS));
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wire rs1_is_fp = is_fr4 || (is_fci && ~(is_fcvtf || (fpu_op == `FPU_MVWX)));
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wire rs2_is_fp = is_fs || is_fr4 || is_fci;
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assign decode_tmp_if.rd = {rd_is_fp, rd};
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assign decode_tmp_if.rs1 = {rs1_is_fp, rs1_qual};
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assign decode_tmp_if.rs2 = {rs2_is_fp, rs2};
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assign decode_tmp_if.rs3 = {1'b1, rs3};
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`else
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assign decode_tmp_if.rd = rd;
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assign decode_tmp_if.rs1 = rs1_qual;
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assign decode_tmp_if.rs2 = rs2;
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assign decode_tmp_if.rs3 = rs3;
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`endif
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assign decode_tmp_if.use_rs3 = use_rs3;
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assign decode_tmp_if.reg_use_mask = ((`NUM_REGS)'(use_rd) << decode_tmp_if.rd)
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| ((`NUM_REGS)'(use_rs1) << decode_tmp_if.rs1)
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| ((`NUM_REGS)'(use_rs2) << decode_tmp_if.rs2)
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| ((`NUM_REGS)'(use_rs3) << decode_tmp_if.rs3);
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assign decode_tmp_if.imm = (is_lui || is_auipc) ? {upper_imm, 12'(0)} :
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(is_jal || is_jalr || is_jals) ? jalx_offset :
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is_csr ? 32'(u_12) :
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src2_imm;
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assign decode_tmp_if.rs1_is_PC = is_auipc;
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assign decode_tmp_if.rs2_is_imm = is_itype || is_lui || is_auipc || is_csr_imm;
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assign decode_tmp_if.frm = func3;
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assign join_if.is_join = in_valid && is_gpu && (gpu_op == `GPU_JOIN);
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assign join_if.warp_num = ifetch_rsp_if.warp_num;
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assign wstall_if.wstall = in_valid && (is_btype || is_jal || is_jalr || (is_gpu && (gpu_op == `GPU_TMC || gpu_op == `GPU_SPLIT || gpu_op == `GPU_BAR)));
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assign wstall_if.warp_num = ifetch_rsp_if.warp_num;
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wire stall = ~decode_if.ready && decode_if.valid;
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VX_generic_register #(
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.N(1 + `NW_BITS + `NUM_THREADS + 32 + 32 + `NR_BITS + `NR_BITS + `NR_BITS + 32 + 1 + `EX_BITS + `OP_BITS + 1 + `NR_BITS + 1 + 1 + `FRM_BITS + `NUM_REGS)
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) decode_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (0),
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.in ({decode_tmp_if.valid, decode_tmp_if.warp_num, decode_tmp_if.thread_mask, decode_tmp_if.curr_PC, decode_tmp_if.next_PC, decode_tmp_if.rd, decode_tmp_if.rs1, decode_tmp_if.rs2, decode_tmp_if.imm, decode_tmp_if.rs1_is_PC, decode_tmp_if.rs2_is_imm, decode_tmp_if.ex_type, decode_tmp_if.ex_op, decode_tmp_if.wb, decode_tmp_if.rs3, decode_tmp_if.use_rs3, decode_tmp_if.frm, decode_tmp_if.reg_use_mask}),
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.out ({decode_if.valid, decode_if.warp_num, decode_if.thread_mask, decode_if.curr_PC, decode_if.next_PC, decode_if.rd, decode_if.rs1, decode_if.rs2, decode_if.imm, decode_if.rs1_is_PC, decode_if.rs2_is_imm, decode_if.ex_type, decode_if.ex_op, decode_if.wb, decode_if.rs3, decode_if.use_rs3, decode_if.frm, decode_if.reg_use_mask})
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);
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assign ifetch_rsp_if.ready = ~stall;
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (decode_tmp_if.valid && ~stall) begin
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$write("%t: Core%0d-Decode: warp=%0d, PC=%0h, ex=", $time, CORE_ID, decode_tmp_if.warp_num, decode_tmp_if.curr_PC);
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print_ex_type(decode_tmp_if.ex_type);
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$write(", op=");
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print_ex_op(decode_tmp_if.ex_type, decode_tmp_if.ex_op);
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$write(", tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=%0h, use_pc=%b, use_imm=%b, frm=", decode_tmp_if.thread_mask, decode_tmp_if.wb, decode_tmp_if.rd, decode_tmp_if.rs1, decode_tmp_if.rs2, decode_tmp_if.rs3, decode_tmp_if.imm, decode_tmp_if.rs1_is_PC, decode_tmp_if.rs2_is_imm);
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print_frm(decode_tmp_if.frm);
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$write("\n");
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// trap unsupported instructions
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assert(~(~stall && (decode_tmp_if.ex_type == `EX_ALU) && `ALU_OP(decode_tmp_if.ex_op) == `ALU_OTHER));
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assert(~(~stall && (decode_tmp_if.ex_type == `EX_CSR) && `CSR_OP(decode_tmp_if.ex_op) == `CSR_OTHER));
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assert(~(~stall && (decode_tmp_if.ex_type == `EX_GPU) && `GPU_OP(decode_tmp_if.ex_op) == `GPU_OTHER));
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end
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end
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`endif
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endmodule |