154 lines
4.5 KiB
Verilog
154 lines
4.5 KiB
Verilog
`include "VX_define.vh"
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module VX_gpr_ram (
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input wire clk,
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input wire [`NUM_THREADS-1:0] we,
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input wire [`NW_BITS+`NR_BITS-1:0] waddr,
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input wire [`NUM_THREADS-1:0][31:0] wdata,
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input wire [`NW_BITS+`NR_BITS-1:0] rs1,
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input wire [`NW_BITS+`NR_BITS-1:0] rs2,
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output wire [`NUM_THREADS-1:0][31:0] rs1_data,
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output wire [`NUM_THREADS-1:0][31:0] rs2_data
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);
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`ifndef ASIC
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reg [`NUM_THREADS-1:0][3:0][7:0] ram [(`NUM_WARPS * `NUM_REGS)-1:0];
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integer i, j;
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initial begin
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// initialize r0 to 0
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for (j = 0; j < `NUM_WARPS; j++) begin
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for (i = 0; i < `NUM_THREADS; i++) begin
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ram[j * `NUM_REGS][i][0] = 8'h0;
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ram[j * `NUM_REGS][i][1] = 8'h0;
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ram[j * `NUM_REGS][i][2] = 8'h0;
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ram[j * `NUM_REGS][i][3] = 8'h0;
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end
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end
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end
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always @(posedge clk) begin
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for (i = 0; i < `NUM_THREADS; i++) begin
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if (we[i]) begin
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ram[waddr][i][0] <= wdata[i][07:00];
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ram[waddr][i][1] <= wdata[i][15:08];
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ram[waddr][i][2] <= wdata[i][23:16];
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ram[waddr][i][3] <= wdata[i][31:24];
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end
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end
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end
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assign rs1_data = ram[rs1];
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assign rs2_data = ram[rs2];
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`else
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wire [`NUM_THREADS-1:0][31:0] write_bit_mask;
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integer i;
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for (i = 0; i < `NUM_THREADS; i++) begin
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assign write_bit_mask[i] = {32{~we[i]}};
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end
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wire cenb = 0;
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wire cena_1 = 0;
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wire cena_2 = 0;
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wire [`NUM_THREADS-1:0][31:0] tmp_a;
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wire [`NUM_THREADS-1:0][31:0] tmp_b;
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`ifndef SYNTHESIS
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integer j;
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for (i = 0; i < `NUM_THREADS; i++) begin
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for (j = 0; j < 32; j++) begin
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assign rs1_data[i][j] = ((tmp_a[i][j] === 1'dx) || cena_1) ? 1'b0 : tmp_a[i][j];
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assign rs2_data[i][j] = ((tmp_b[i][j] === 1'dx) || cena_2) ? 1'b0 : tmp_b[i][j];
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end
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end
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`else
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assign rs1_data = tmp_a;
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assign rs2_data = tmp_b;
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`endif
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for (i = 0; i < 'NT; i=i+4) begin
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`IGNORE_WARNINGS_BEGIN
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rf2_32x128_wm1 first_ram (
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.CENYA(),
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.AYA(),
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.CENYB(),
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.WENYB(),
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.AYB(),
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.QA(tmp_a[(i+3):(i)]),
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.SOA(),
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.SOB(),
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.CLKA(clk),
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.CENA(cena_1),
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.AA(rs1[(i+3):(i)]),
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.CLKB(clk),
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.CENB(cenb),
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.WENB(write_bit_mask[(i+3):(i)]),
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.AB(waddr[(i+3):(i)]),
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.DB(wdata[(i+3):(i)]),
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.EMAA(3'b011),
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.EMASA(1'b0),
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.EMAB(3'b011),
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.TENA(1'b1),
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.TCENA(1'b0),
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.TAA(5'b0),
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.TENB(1'b1),
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.TCENB(1'b0),
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.TWENB(128'b0),
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.TAB(5'b0),
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.TDB(128'b0),
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.RET1N(1'b1),
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.SIA(2'b0),
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.SEA(1'b0),
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.DFTRAMBYP(1'b0),
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.SIB(2'b0),
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.SEB(1'b0),
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.COLLDISN(1'b1)
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);
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rf2_`NUM_GPRSx128_wm1 second_ram (
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.CENYA(),
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.AYA(),
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.CENYB(),
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.WENYB(),
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.AYB(),
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.QA(tmp_b[(i+3):(i)]),
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.SOA(),
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.SOB(),
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.CLKA(clk),
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.CENA(cena_2),
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.AA(rs2[(i+3):(i)]),
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.CLKB(clk),
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.CENB(cenb),
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.WENB(write_bit_mask[(i+3):(i)]),
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.AB(waddr[(i+3):(i)]),
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.DB(wdata[(i+3):(i)]),
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.EMAA(3'b011),
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.EMASA(1'b0),
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.EMAB(3'b011),
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.TENA(1'b1),
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.TCENA(1'b0),
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.TAA(5'b0),
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.TENB(1'b1),
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.TCENB(1'b0),
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.TWENB(128'b0),
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.TAB(5'b0),
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.TDB(128'b0),
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.RET1N(1'b1),
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.SIA(2'b0),
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.SEA(1'b0),
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.DFTRAMBYP(1'b0),
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.SIB(2'b0),
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.SEB(1'b0),
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.COLLDISN(1'b1)
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);
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`IGNORE_WARNINGS_END
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end
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`endif
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endmodule
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