118 lines
6.3 KiB
Verilog
118 lines
6.3 KiB
Verilog
`include "VX_define.vh"
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module VX_issue #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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VX_decode_if decode_if,
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VX_wb_if writeback_if,
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VX_cmt_to_issue_if cmt_to_issue_if,
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VX_alu_req_if alu_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_mul_req_if mul_req_if,
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VX_fpu_req_if fpu_req_if,
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VX_gpu_req_if gpu_req_if
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);
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VX_gpr_read_if gpr_read_if();
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assign gpr_read_if.valid = decode_if.valid;
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assign gpr_read_if.warp_num = decode_if.warp_num;
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assign gpr_read_if.rs1 = decode_if.rs1;
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assign gpr_read_if.rs2 = decode_if.rs2;
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assign gpr_read_if.rs3 = decode_if.rs3;
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assign gpr_read_if.use_rs3 = decode_if.use_rs3;
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assign gpr_read_if.out_ready = decode_if.ready;
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wire [`ISTAG_BITS-1:0] issue_tag, issue_tmp_tag;
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wire gpr_busy = ~gpr_read_if.in_ready;
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wire alu_busy = ~alu_req_if.ready;
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wire lsu_busy = ~lsu_req_if.ready;
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wire csr_busy = ~csr_req_if.ready;
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wire mul_busy = ~mul_req_if.ready;
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wire fpu_busy = ~mul_req_if.ready;
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wire gpu_busy = ~gpu_req_if.ready;
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VX_scheduler #(
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.CORE_ID(CORE_ID)
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) scheduler (
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.clk (clk),
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.reset (reset),
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.decode_if (decode_if),
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.writeback_if (writeback_if),
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.cmt_to_issue_if(cmt_to_issue_if),
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.gpr_busy (gpr_busy),
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.alu_busy (alu_busy),
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.lsu_busy (lsu_busy),
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.csr_busy (csr_busy),
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.mul_busy (mul_busy),
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.fpu_busy (fpu_busy),
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.gpu_busy (gpu_busy),
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.issue_tag (issue_tag)
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);
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VX_gpr_stage #(
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.CORE_ID(CORE_ID)
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) gpr_stage (
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.clk (clk),
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.reset (reset),
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.writeback_if (writeback_if),
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.gpr_read_if (gpr_read_if)
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);
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VX_decode_if decode_tmp_if();
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VX_gpr_read_if gpr_read_tmp_if();
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wire stall = ~alu_req_if.ready || ~decode_if.ready;
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wire flush = alu_req_if.ready && ~decode_if.ready;
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VX_generic_register #(
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.N(1 + `ISTAG_BITS + `NW_BITS + `NUM_THREADS + 32 + 32 + `NR_BITS + `NR_BITS + `NR_BITS + 32 + 1 + 1 + `EX_BITS + `OP_BITS + 1 + `NR_BITS + 1 + `FRM_BITS + (`NUM_THREADS * 32) + (`NUM_THREADS * 32) + (`NUM_THREADS * 32))
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) issue_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (flush),
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.in ({decode_if.valid, issue_tag, decode_if.warp_num, decode_if.thread_mask, decode_if.curr_PC, decode_if.next_PC, decode_if.rd, decode_if.rs1, decode_if.rs2, decode_if.imm, decode_if.rs1_is_PC, decode_if.rs2_is_imm, decode_if.ex_type, decode_if.ex_op, decode_if.wb, decode_if.rs3, decode_if.use_rs3, decode_if.frm, gpr_read_if.rs1_data, gpr_read_if.rs2_data, gpr_read_if.rs3_data}),
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.out ({decode_tmp_if.valid, issue_tmp_tag, decode_tmp_if.warp_num, decode_tmp_if.thread_mask, decode_tmp_if.curr_PC, decode_tmp_if.next_PC, decode_tmp_if.rd, decode_tmp_if.rs1, decode_tmp_if.rs2, decode_tmp_if.imm, decode_tmp_if.rs1_is_PC, decode_tmp_if.rs2_is_imm, decode_tmp_if.ex_type, decode_tmp_if.ex_op, decode_tmp_if.wb, decode_tmp_if.rs3, decode_tmp_if.use_rs3, decode_tmp_if.frm, gpr_read_tmp_if.rs1_data, gpr_read_tmp_if.rs2_data, gpr_read_tmp_if.rs3_data})
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);
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VX_issue_demux issue_demux (
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.decode_if (decode_tmp_if),
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.gpr_read_if (gpr_read_tmp_if),
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.issue_tag (issue_tmp_tag),
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.alu_req_if (alu_req_if),
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.lsu_req_if (lsu_req_if),
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.csr_req_if (csr_req_if),
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.mul_req_if (mul_req_if),
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.fpu_req_if (fpu_req_if),
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.gpu_req_if (gpu_req_if)
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);
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (alu_req_if.valid && alu_req_if.ready) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=ALU, istag=%0d, tmask=%b, wb=%d, rd=%0d, rs1_data=%0h, rs2_data=%0h, offset=%0h, next_PC=%0h", $time, CORE_ID, decode_tmp_if.warp_num, decode_tmp_if.curr_PC, issue_tmp_tag, decode_tmp_if.thread_mask, decode_tmp_if.wb, decode_tmp_if.rd, alu_req_if.rs1_data, alu_req_if.rs2_data, alu_req_if.offset, alu_req_if.next_PC);
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end
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if (lsu_req_if.valid && lsu_req_if.ready) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=LSU, istag=%0d, tmask=%b, wb=%0b, rd=%0d, rw=%b, byteen=%b, baddr=%0h, offset=%0h, data=%0h", $time, CORE_ID, decode_tmp_if.warp_num, decode_tmp_if.curr_PC, issue_tmp_tag, decode_tmp_if.thread_mask, decode_tmp_if.wb, decode_tmp_if.rd, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.base_addr, lsu_req_if.offset, lsu_req_if.store_data);
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end
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if (csr_req_if.valid && csr_req_if.ready) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=CSR, istag=%0d, tmask=%b, wb=%d, rd=%0d, addr=%0h, mask=%0h", $time, CORE_ID, decode_tmp_if.warp_num, decode_tmp_if.curr_PC, issue_tmp_tag, decode_tmp_if.thread_mask, decode_tmp_if.wb, decode_tmp_if.rd, csr_req_if.csr_addr, csr_req_if.csr_mask);
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end
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if (mul_req_if.valid && mul_req_if.ready) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=MUL, istag=%0d, tmask=%b, wb=%d, rd=%0d, rs1_data=%0h, rs2_data=%0h", $time, CORE_ID, decode_tmp_if.warp_num, decode_tmp_if.curr_PC, issue_tmp_tag, decode_tmp_if.thread_mask, decode_tmp_if.wb, decode_tmp_if.rd, mul_req_if.rs1_data, mul_req_if.rs2_data);
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end
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if (fpu_req_if.valid && fpu_req_if.ready) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=FPU, istag=%0d, tmask=%b, wb=%d, rd=%0d, frm=%0h, rs1_data=%0h, rs2_data=%0h, rs3_data=%0h", $time, CORE_ID, decode_tmp_if.warp_num, decode_tmp_if.curr_PC, issue_tmp_tag, decode_tmp_if.thread_mask, decode_tmp_if.wb, decode_tmp_if.rd, fpu_req_if.frm, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data);
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end
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if (gpu_req_if.valid && gpu_req_if.ready) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=GPU, istag=%0d, tmask=%b, rs1_data=%0h, rs2_data=%0h", $time, CORE_ID, decode_tmp_if.warp_num, decode_tmp_if.curr_PC, issue_tmp_tag, decode_tmp_if.thread_mask, gpu_req_if.rs1_data, gpu_req_if.rs2_data);
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end
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end
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`endif
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endmodule |