138 lines
4.3 KiB
Verilog
138 lines
4.3 KiB
Verilog
`include "VX_define.vh"
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module VX_mul_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// Inputs
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VX_mul_req_if alu_req_if,
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// Outputs
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VX_exu_to_cmt_if alu_commit_if
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);
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wire [`MUL_BITS-1:0] alu_op = alu_req_if.mul_op;
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wire [`NUM_THREADS-1:0][31:0] alu_in1 = alu_req_if.rs1_data;
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wire [`NUM_THREADS-1:0][31:0] alu_in2 = alu_req_if.rs2_data;
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wire [`NUM_THREADS-1:0][31:0] mul_result, div_result;
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wire stall_mul, stall_div;
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wire is_mul_op = (alu_op == `MUL_MUL);
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wire is_div_op = (alu_op == `MUL_DIV || alu_op == `MUL_DIVU);
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reg [`NUM_THREADS-1:0] is_div_op_in;
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wire [`NUM_THREADS-1:0] is_div_op_out;
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wire is_mul_op_out;
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genvar i;
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for (i = 0; i < `NUM_THREADS; i++) begin
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wire [32:0] mul_in1 = {(alu_op != `MUL_MULHU) & alu_in1[i][31], alu_in1[i]};
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wire [32:0] mul_in2 = {(alu_op != `MUL_MULHU && alu_op != `MUL_MULHSU) & alu_in2[i][31], alu_in2[i]};
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reg [32:0] div_in1, div_in2;
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// handle divide by zero
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always @(*) begin
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is_div_op_in[i] = is_div_op;
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div_in1 = {(alu_op == `MUL_DIV || alu_op == `MUL_REM) & alu_in1[i][31], alu_in1[i]};
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div_in2 = {(alu_op == `MUL_DIV || alu_op == `MUL_REM) & alu_in2[i][31], alu_in2[i]};
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if (0 == alu_in2[i]) begin
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if (is_div_op) begin
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div_in1 = {1'b0, 32'hFFFFFFFF}; // quotient = (0xFFFFFFFF / 1)
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div_in2 = 1;
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end else begin
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is_div_op_in[i] = 1; // remainder = (in1 / 1)
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div_in2 = 1;
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end
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end
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end
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wire [63:0] mul_result_tmp;
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wire [31:0] div_result_tmp;
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wire [31:0] rem_result_tmp;
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VX_multiplier #(
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.WIDTHA(33),
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.WIDTHB(33),
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.WIDTHP(64),
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.SIGNED(1),
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.PIPELINE(`LATENCY_IMUL)
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) multiplier (
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.clk(clk),
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.reset(reset),
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.clk_en(~stall_mul),
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.dataa(mul_in1),
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.datab(mul_in2),
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.result(mul_result_tmp)
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);
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VX_divide #(
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.WIDTHN(33),
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.WIDTHD(33),
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.WIDTHQ(32),
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.WIDTHR(32),
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.NSIGNED(1),
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.DSIGNED(1),
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.PIPELINE(`LATENCY_IDIV)
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) divide (
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.clk(clk),
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.reset(reset),
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.clk_en(~stall_div),
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.numer(div_in1),
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.denom(div_in2),
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.quotient(div_result_tmp),
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.remainder(rem_result_tmp)
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);
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assign mul_result[i] = is_mul_op_out ? mul_result_tmp[31:0] : mul_result_tmp[63:32];
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assign div_result[i] = is_div_op_out[i] ? div_result_tmp : rem_result_tmp;
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end
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wire mul_valid_out;
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wire div_valid_out;
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wire [`ISTAG_BITS-1:0] mul_issue_tag;
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wire [`ISTAG_BITS-1:0] div_issue_tag;
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VX_shift_register #(
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.DATAW(1 + `ISTAG_BITS + 1),
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.DEPTH(`LATENCY_IMUL)
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) mul_delay (
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.clk(clk),
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.reset(reset),
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.enable(~stall_mul),
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.in({alu_req_if.valid && ~`IS_DIV_OP(alu_op), alu_req_if.issue_tag, is_mul_op}),
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.out({mul_valid_out, mul_issue_tag, is_mul_op_out})
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);
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VX_shift_register #(
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.DATAW(1 + `ISTAG_BITS + `NUM_THREADS),
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.DEPTH(`LATENCY_IDIV)
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) div_delay (
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.clk(clk),
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.reset(reset),
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.enable(~stall_div),
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.in({alu_req_if.valid && `IS_DIV_OP(alu_op), alu_req_if.issue_tag, is_div_op_in}),
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.out({div_valid_out, div_issue_tag, is_div_op_out})
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);
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wire stall_out = (~alu_commit_if.ready && alu_commit_if.valid);
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assign stall_mul = stall_out;
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assign stall_div = stall_out
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|| (mul_valid_out && div_valid_out); // arbitration prioritizes MUL
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// can accept new request?
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assign alu_req_if.ready = ~(stall_mul || stall_div);
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assign alu_commit_if.valid = mul_valid_out || div_valid_out;
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assign alu_commit_if.issue_tag = mul_valid_out ? mul_issue_tag : div_issue_tag;
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assign alu_commit_if.data = mul_valid_out ? mul_result : div_result;
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endmodule |